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net/qede/base: add new files and rearrange the code

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Added ecore_hsi_debug_tools.h, ecore_hsi_init_func.h,
ecore_hsi_init_tool.h files. Rearranged code from ecore_hsi_common.h and
ecore_hsi_tools.h to the new files. Removed unused code.

Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
This commit is contained in:
Rasesh Mody 2016-10-18 21:11:15 -07:00 committed by Bruce Richardson
parent 69491883cb
commit c018d2b49d
10 changed files with 1677 additions and 1539 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/net/qede/base/ecore.h
View File

@ -10,7 +10,9 @@
#define __ECORE_H
#include "ecore_hsi_common.h"
#include "ecore_hsi_tools.h"
#include "ecore_hsi_debug_tools.h"
#include "ecore_hsi_init_func.h"
#include "ecore_hsi_init_tool.h"
#include "ecore_proto_if.h"
#include "mcp_public.h"
@ -556,14 +558,15 @@ struct ecore_dev {
#define ECORE_DEV_TYPE_AH (1 << 0)
/* Translate type/revision combo into the proper conditions */
#define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
#define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && \
CHIP_REV_IS_A0(dev))
#define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && \
CHIP_REV_IS_B0(dev))
#define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
#ifndef ASIC_ONLY
#define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
(CHIP_REV_IS_TEDIBEAR(dev)))
#else
#define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
#endif
#define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
#define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
#define ECORE_GET_TYPE(dev) (ECORE_IS_BB_A0(dev) ? CHIP_BB_A0 : \
ECORE_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
u16 vendor_id;
u16 device_id;

73
drivers/net/qede/base/ecore_dev.c
View File

@ -281,13 +281,6 @@ static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
for (i = 0; i < num_ports; i++) {
p_qm_port = &qm_info->qm_port_params[i];
p_qm_port->active = 1;
/* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
* be in place
*/
if (num_ports == 4)
p_qm_port->num_active_phys_tcs = 2;
else
p_qm_port->num_active_phys_tcs = 5;
p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
}
@ -599,19 +592,15 @@ static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
{
int hw_mode = 0;
switch (ECORE_GET_TYPE(p_hwfn->p_dev)) {
case CHIP_BB_A0:
if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_BB_A0;
break;
case CHIP_BB_B0:
} else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_BB_B0;
break;
case CHIP_K2:
} else if (ECORE_IS_AH(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_K2;
break;
default:
DP_NOTICE(p_hwfn, true, "Can't initialize chip ID %d\n",
ECORE_GET_TYPE(p_hwfn->p_dev));
} else {
DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
p_hwfn->p_dev->type);
return;
}
@ -690,37 +679,6 @@ static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
/* initialize interrupt masks */
for (i = 0;
i <
attn_blocks[BLOCK_MISCS].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
num_of_int_regs; i++)
ecore_wr(p_hwfn, p_ptt,
attn_blocks[BLOCK_MISCS].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[i]->
mask_addr, 0);
if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
ecore_wr(p_hwfn, p_ptt,
attn_blocks[BLOCK_CNIG].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
mask_addr, 0);
ecore_wr(p_hwfn, p_ptt,
attn_blocks[BLOCK_PGLCS].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
mask_addr, 0);
ecore_wr(p_hwfn, p_ptt,
attn_blocks[BLOCK_CPMU].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
mask_addr, 0);
/* Currently A0 and B0 interrupt bits are the same in pglue_b;
* If this changes, need to set this according to chip type. <14/09/23>
*/
ecore_wr(p_hwfn, p_ptt,
attn_blocks[BLOCK_PGLUE_B].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
mask_addr, 0x80000);
/* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
/* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
@ -1227,25 +1185,6 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
* &ctrl);
*/
#ifndef ASIC_ONLY
/*@@TMP - On B0 build 1, need to mask the datapath_registers parity */
if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev) &&
(p_hwfn->p_dev->chip_metal == 1)) {
u32 reg_addr, tmp;
reg_addr =
attn_blocks[BLOCK_PGLUE_B].
chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].prty_regs[0]->
mask_addr;
DP_NOTICE(p_hwfn, false,
"Masking datapath registers parity on"
" B0 emulation [build 1]\n");
tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
tmp |= (1 << 0); /* Was PRTY_MASK_DATAPATH_REGISTERS */
ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
}
#endif
rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
if (rc)
return rc;

226
drivers/net/qede/base/ecore_hsi_common.h
View File

@ -1319,172 +1319,6 @@ struct atten_status_block {
__le32 reserved1;
};
enum block_addr {
GRCBASE_GRC = 0x50000,
GRCBASE_MISCS = 0x9000,
GRCBASE_MISC = 0x8000,
GRCBASE_DBU = 0xa000,
GRCBASE_PGLUE_B = 0x2a8000,
GRCBASE_CNIG = 0x218000,
GRCBASE_CPMU = 0x30000,
GRCBASE_NCSI = 0x40000,
GRCBASE_OPTE = 0x53000,
GRCBASE_BMB = 0x540000,
GRCBASE_PCIE = 0x54000,
GRCBASE_MCP = 0xe00000,
GRCBASE_MCP2 = 0x52000,
GRCBASE_PSWHST = 0x2a0000,
GRCBASE_PSWHST2 = 0x29e000,
GRCBASE_PSWRD = 0x29c000,
GRCBASE_PSWRD2 = 0x29d000,
GRCBASE_PSWWR = 0x29a000,
GRCBASE_PSWWR2 = 0x29b000,
GRCBASE_PSWRQ = 0x280000,
GRCBASE_PSWRQ2 = 0x240000,
GRCBASE_PGLCS = 0x0,
GRCBASE_DMAE = 0xc000,
GRCBASE_PTU = 0x560000,
GRCBASE_TCM = 0x1180000,
GRCBASE_MCM = 0x1200000,
GRCBASE_UCM = 0x1280000,
GRCBASE_XCM = 0x1000000,
GRCBASE_YCM = 0x1080000,
GRCBASE_PCM = 0x1100000,
GRCBASE_QM = 0x2f0000,
GRCBASE_TM = 0x2c0000,
GRCBASE_DORQ = 0x100000,
GRCBASE_BRB = 0x340000,
GRCBASE_SRC = 0x238000,
GRCBASE_PRS = 0x1f0000,
GRCBASE_TSDM = 0xfb0000,
GRCBASE_MSDM = 0xfc0000,
GRCBASE_USDM = 0xfd0000,
GRCBASE_XSDM = 0xf80000,
GRCBASE_YSDM = 0xf90000,
GRCBASE_PSDM = 0xfa0000,
GRCBASE_TSEM = 0x1700000,
GRCBASE_MSEM = 0x1800000,
GRCBASE_USEM = 0x1900000,
GRCBASE_XSEM = 0x1400000,
GRCBASE_YSEM = 0x1500000,
GRCBASE_PSEM = 0x1600000,
GRCBASE_RSS = 0x238800,
GRCBASE_TMLD = 0x4d0000,
GRCBASE_MULD = 0x4e0000,
GRCBASE_YULD = 0x4c8000,
GRCBASE_XYLD = 0x4c0000,
GRCBASE_PRM = 0x230000,
GRCBASE_PBF_PB1 = 0xda0000,
GRCBASE_PBF_PB2 = 0xda4000,
GRCBASE_RPB = 0x23c000,
GRCBASE_BTB = 0xdb0000,
GRCBASE_PBF = 0xd80000,
GRCBASE_RDIF = 0x300000,
GRCBASE_TDIF = 0x310000,
GRCBASE_CDU = 0x580000,
GRCBASE_CCFC = 0x2e0000,
GRCBASE_TCFC = 0x2d0000,
GRCBASE_IGU = 0x180000,
GRCBASE_CAU = 0x1c0000,
GRCBASE_UMAC = 0x51000,
GRCBASE_XMAC = 0x210000,
GRCBASE_DBG = 0x10000,
GRCBASE_NIG = 0x500000,
GRCBASE_WOL = 0x600000,
GRCBASE_BMBN = 0x610000,
GRCBASE_IPC = 0x20000,
GRCBASE_NWM = 0x800000,
GRCBASE_NWS = 0x700000,
GRCBASE_MS = 0x6a0000,
GRCBASE_PHY_PCIE = 0x620000,
GRCBASE_MISC_AEU = 0x8000,
GRCBASE_BAR0_MAP = 0x1c00000,
MAX_BLOCK_ADDR
};
enum block_id {
BLOCK_GRC,
BLOCK_MISCS,
BLOCK_MISC,
BLOCK_DBU,
BLOCK_PGLUE_B,
BLOCK_CNIG,
BLOCK_CPMU,
BLOCK_NCSI,
BLOCK_OPTE,
BLOCK_BMB,
BLOCK_PCIE,
BLOCK_MCP,
BLOCK_MCP2,
BLOCK_PSWHST,
BLOCK_PSWHST2,
BLOCK_PSWRD,
BLOCK_PSWRD2,
BLOCK_PSWWR,
BLOCK_PSWWR2,
BLOCK_PSWRQ,
BLOCK_PSWRQ2,
BLOCK_PGLCS,
BLOCK_DMAE,
BLOCK_PTU,
BLOCK_TCM,
BLOCK_MCM,
BLOCK_UCM,
BLOCK_XCM,
BLOCK_YCM,
BLOCK_PCM,
BLOCK_QM,
BLOCK_TM,
BLOCK_DORQ,
BLOCK_BRB,
BLOCK_SRC,
BLOCK_PRS,
BLOCK_TSDM,
BLOCK_MSDM,
BLOCK_USDM,
BLOCK_XSDM,
BLOCK_YSDM,
BLOCK_PSDM,
BLOCK_TSEM,
BLOCK_MSEM,
BLOCK_USEM,
BLOCK_XSEM,
BLOCK_YSEM,
BLOCK_PSEM,
BLOCK_RSS,
BLOCK_TMLD,
BLOCK_MULD,
BLOCK_YULD,
BLOCK_XYLD,
BLOCK_PRM,
BLOCK_PBF_PB1,
BLOCK_PBF_PB2,
BLOCK_RPB,
BLOCK_BTB,
BLOCK_PBF,
BLOCK_RDIF,
BLOCK_TDIF,
BLOCK_CDU,
BLOCK_CCFC,
BLOCK_TCFC,
BLOCK_IGU,
BLOCK_CAU,
BLOCK_UMAC,
BLOCK_XMAC,
BLOCK_DBG,
BLOCK_NIG,
BLOCK_WOL,
BLOCK_BMBN,
BLOCK_IPC,
BLOCK_NWM,
BLOCK_NWS,
BLOCK_MS,
BLOCK_PHY_PCIE,
BLOCK_MISC_AEU,
BLOCK_BAR0_MAP,
MAX_BLOCK_ID
};
/*
* Igu cleanup bit values to distinguish between clean or producer consumer
*/
@ -1561,43 +1395,12 @@ struct dmae_cmd {
__le16 xsum8 /* checksum8 result */;
};
struct fw_ver_num {
u8 major /* Firmware major version number */;
u8 minor /* Firmware minor version number */;
u8 rev /* Firmware revision version number */;
u8 eng /* Firmware engineering version number (for bootleg versions) */
;
};
struct fw_ver_info {
__le16 tools_ver /* Tools version number */;
u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
u8 reserved1;
struct fw_ver_num num /* FW version number */;
__le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
__le32 reserved2;
};
struct storm_ram_section {
__le16 offset
/* The offset of the section in the RAM (in 64 bit units) */;
__le16 size /* The size of the section (in 64 bit units) */;
};
struct fw_info {
struct fw_ver_info ver /* FW version information */;
struct storm_ram_section fw_asserts_section
/* The FW Asserts offset/size in Storm RAM */;
__le32 reserved;
};
struct fw_info_location {
__le32 grc_addr /* GRC address where the fw_info struct is located. */;
__le32 size
/* Size of the fw_info structure (thats located at the grc_addr). */
;
};
/*
* IGU cleanup command
*/
@ -1672,35 +1475,6 @@ struct igu_msix_vector {
#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
};
enum init_modes {
MODE_BB_A0,
MODE_BB_B0,
MODE_K2,
MODE_ASIC,
MODE_EMUL_REDUCED,
MODE_EMUL_FULL,
MODE_FPGA,
MODE_CHIPSIM,
MODE_SF,
MODE_MF_SD,
MODE_MF_SI,
MODE_PORTS_PER_ENG_1,
MODE_PORTS_PER_ENG_2,
MODE_PORTS_PER_ENG_4,
MODE_100G,
MODE_EAGLE_ENG1_WORKAROUND,
MAX_INIT_MODES
};
enum init_phases {
PHASE_ENGINE,
PHASE_PORT,
PHASE_PF,
PHASE_VF,
PHASE_QM_PF,
MAX_INIT_PHASES
};
struct mstorm_core_conn_ag_ctx {
u8 byte0 /* cdu_validation */;
u8 byte1 /* state */;

1025
drivers/net/qede/base/ecore_hsi_debug_tools.h Normal file
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File diff suppressed because it is too large Load Diff

132
drivers/net/qede/base/ecore_hsi_init_func.h Normal file
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@ -0,0 +1,132 @@
/*
* Copyright (c) 2016 QLogic Corporation.
* All rights reserved.
* www.qlogic.com
*
* See LICENSE.qede_pmd for copyright and licensing details.
*/
#ifndef __ECORE_HSI_INIT_FUNC__
#define __ECORE_HSI_INIT_FUNC__
/********************************/
/* HSI Init Functions constants */
/********************************/
/* Number of VLAN priorities */
#define NUM_OF_VLAN_PRIORITIES 8
/*
* BRB RAM init requirements
*/
struct init_brb_ram_req {
__le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;
__le32 headroom_per_tc /* headroom size per TC, in bytes */;
__le32 min_pkt_size /* min packet size, in bytes */;
__le32 max_ports_per_engine /* min packet size, in bytes */;
u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;
};
/*
* ETS per-TC init requirements
*/
struct init_ets_tc_req {
/* if set, this TC participates in the arbitration with a strict priority
* (the priority is equal to the TC ID)
*/
u8 use_sp;
/* if set, this TC participates in the arbitration with a WFQ weight
* (indicated by the weight field)
*/
u8 use_wfq;
/* An arbitration weight. Valid only if use_wfq is set. */
__le16 weight;
};
/*
* ETS init requirements
*/
struct init_ets_req {
__le32 mtu /* Max packet size (in bytes) */;
/* ETS initialization requirements per TC. */
struct init_ets_tc_req tc_req[NUM_OF_TCS];
};
/*
* NIG LB RL init requirements
*/
struct init_nig_lb_rl_req {
/* Global MAC+LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
__le16 lb_mac_rate;
/* Global LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
__le16 lb_rate;
__le32 mtu /* Max packet size (in bytes) */;
/* RL rate per physical TC (in Mbps). If set to 0, the RL will be disabled. */
__le16 tc_rate[NUM_OF_PHYS_TCS];
};
/*
* NIG TC mapping for each priority
*/
struct init_nig_pri_tc_map_entry {
u8 tc_id /* the mapped TC ID */;
u8 valid /* indicates if the mapping entry is valid */;
};
/*
* NIG priority to TC map init requirements
*/
struct init_nig_pri_tc_map_req {
struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
};
/*
* QM per-port init parameters
*/
struct init_qm_port_params {
u8 active /* Indicates if this port is active */;
/* Vector of valid bits for active TCs used by this port */
u8 active_phys_tcs;
/* number of PBF command lines that can be used by this port */
__le16 num_pbf_cmd_lines;
/* number of BTB blocks that can be used by this port */
__le16 num_btb_blocks;
__le16 reserved;
};
/*
* QM per-PQ init parameters
*/
struct init_qm_pq_params {
u8 vport_id /* VPORT ID */;
u8 tc_id /* TC ID */;
u8 wrr_group /* WRR group */;
/* Indicates if a rate limiter should be allocated for the PQ (0/1) */
u8 rl_valid;
};
/*
* QM per-vport init parameters
*/
struct init_qm_vport_params {
/* rate limit in Mb/sec units. a value of 0 means dont configure. ignored if
* VPORT RL is globally disabled.
*/
__le32 vport_rl;
/* WFQ weight. A value of 0 means dont configure. ignored if VPORT WFQ is
* globally disabled.
*/
__le16 vport_wfq;
/* the first Tx PQ ID associated with this VPORT for each TC. */
__le16 first_tx_pq_id[NUM_OF_TCS];
};
#endif /* __ECORE_HSI_INIT_FUNC__ */

454
drivers/net/qede/base/ecore_hsi_init_tool.h Normal file
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@ -0,0 +1,454 @@
/*
* Copyright (c) 2016 QLogic Corporation.
* All rights reserved.
* www.qlogic.com
*
* See LICENSE.qede_pmd for copyright and licensing details.
*/
#ifndef __ECORE_HSI_INIT_TOOL__
#define __ECORE_HSI_INIT_TOOL__
/**************************************/
/* Init Tool HSI constants and macros */
/**************************************/
/* Width of GRC address in bits (addresses are specified in dwords) */
#define GRC_ADDR_BITS 23
#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
/* indicates an init that should be applied to any phase ID */
#define ANY_PHASE_ID 0xffff
/* Max size in dwords of a zipped array */
#define MAX_ZIPPED_SIZE 8192
struct fw_asserts_ram_section {
/* The offset of the section in the RAM in RAM lines (64-bit units) */
__le16 section_ram_line_offset;
/* The size of the section in RAM lines (64-bit units) */
__le16 section_ram_line_size;
/* The offset of the asserts list within the section in dwords */
u8 list_dword_offset;
/* The size of an assert list element in dwords */
u8 list_element_dword_size;
u8 list_num_elements /* The number of elements in the asserts list */;
/* The offset of the next list index field within the section in dwords */
u8 list_next_index_dword_offset;
};
struct fw_ver_num {
u8 major /* Firmware major version number */;
u8 minor /* Firmware minor version number */;
u8 rev /* Firmware revision version number */;
/* Firmware engineering version number (for bootleg versions) */
u8 eng;
};
struct fw_ver_info {
__le16 tools_ver /* Tools version number */;
u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
u8 reserved1;
struct fw_ver_num num /* FW version number */;
__le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
__le32 reserved2;
};
struct fw_info {
struct fw_ver_info ver /* FW version information */;
/* Info regarding the FW asserts section in the Storm RAM */
struct fw_asserts_ram_section fw_asserts_section;
};
struct fw_info_location {
/* GRC address where the fw_info struct is located. */
__le32 grc_addr;
/* Size of the fw_info structure (thats located at the grc_addr). */
__le32 size;
};
enum init_modes {
MODE_BB_A0,
MODE_BB_B0,
MODE_K2,
MODE_ASIC,
MODE_EMUL_REDUCED,
MODE_EMUL_FULL,
MODE_FPGA,
MODE_CHIPSIM,
MODE_SF,
MODE_MF_SD,
MODE_MF_SI,
MODE_PORTS_PER_ENG_1,
MODE_PORTS_PER_ENG_2,
MODE_PORTS_PER_ENG_4,
MODE_100G,
MODE_40G,
MODE_EAGLE_ENG1_WORKAROUND,
MAX_INIT_MODES
};
enum init_phases {
PHASE_ENGINE,
PHASE_PORT,
PHASE_PF,
PHASE_VF,
PHASE_QM_PF,
MAX_INIT_PHASES
};
enum init_split_types {
SPLIT_TYPE_NONE,
SPLIT_TYPE_PORT,
SPLIT_TYPE_PF,
SPLIT_TYPE_PORT_PF,
SPLIT_TYPE_VF,
MAX_INIT_SPLIT_TYPES
};
/*
* Binary buffer header
*/
struct bin_buffer_hdr {
/* buffer offset in bytes from the beginning of the binary file */
__le32 offset;
__le32 length /* buffer length in bytes */;
};
/*
* binary init buffer types
*/
enum bin_init_buffer_type {
BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
BIN_BUF_INIT_CMD /* init commands */,
BIN_BUF_INIT_VAL /* init data */,
BIN_BUF_INIT_MODE_TREE /* init modes tree */,
BIN_BUF_INIT_IRO /* internal RAM offsets */,
MAX_BIN_INIT_BUFFER_TYPE
};
/*
* init array header: raw
*/
struct init_array_raw_hdr {
__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
/* init array params */
#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
};
/*
* init array header: standard
*/
struct init_array_standard_hdr {
__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
/* Init array size (in dwords) */
#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
};
/*
* init array header: zipped
*/
struct init_array_zipped_hdr {
__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
/* Init array zipped size (in bytes) */
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
};
/*
* init array header: pattern
*/
struct init_array_pattern_hdr {
__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
/* pattern size in dword */
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
/* pattern repetitions */
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
};
/*
* init array header union
*/
union init_array_hdr {
struct init_array_raw_hdr raw /* raw init array header */;
/* standard init array header */
struct init_array_standard_hdr standard;
struct init_array_zipped_hdr zipped /* zipped init array header */;
struct init_array_pattern_hdr pattern /* pattern init array header */;
};
/*
* init array types
*/
enum init_array_types {
INIT_ARR_STANDARD /* standard init array */,
INIT_ARR_ZIPPED /* zipped init array */,
INIT_ARR_PATTERN /* a repeated pattern */,
MAX_INIT_ARRAY_TYPES
};
/*
* init operation: callback
*/
struct init_callback_op {
__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_CALLBACK_OP_OP_MASK 0xF
#define INIT_CALLBACK_OP_OP_SHIFT 0
#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
__le16 callback_id /* Callback ID */;
__le16 block_id /* Blocks ID */;
};
/*
* init operation: delay
*/
struct init_delay_op {
__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_DELAY_OP_OP_MASK 0xF
#define INIT_DELAY_OP_OP_SHIFT 0
#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
#define INIT_DELAY_OP_RESERVED_SHIFT 4
__le32 delay /* delay in us */;
};
/*
* init operation: if_mode
*/
struct init_if_mode_op {
__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_IF_MODE_OP_OP_MASK 0xF
#define INIT_IF_MODE_OP_OP_SHIFT 0
#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
/* Commands to skip if the modes dont match */
#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
__le16 reserved2;
/* offset (in bytes) in modes expression buffer */
__le16 modes_buf_offset;
};
/*
* init operation: if_phase
*/
struct init_if_phase_op {
__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_IF_PHASE_OP_OP_MASK 0xF
#define INIT_IF_PHASE_OP_OP_SHIFT 0
/* Indicates if DMAE is enabled in this phase */
#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
/* Commands to skip if the phases dont match */
#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
__le32 phase_data;
#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
};
/*
* init mode operators
*/
enum init_mode_ops {
INIT_MODE_OP_NOT /* init mode not operator */,
INIT_MODE_OP_OR /* init mode or operator */,
INIT_MODE_OP_AND /* init mode and operator */,
MAX_INIT_MODE_OPS
};
/*
* init operation: raw
*/
struct init_raw_op {
__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_RAW_OP_OP_MASK 0xF
#define INIT_RAW_OP_OP_SHIFT 0
#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
#define INIT_RAW_OP_PARAM1_SHIFT 4
__le32 param2 /* Init param 2 */;
};
/*
* init array params
*/
struct init_op_array_params {
__le16 size /* array size in dwords */;
__le16 offset /* array start offset in dwords */;
};
/*
* Write init operation arguments
*/
union init_write_args {
/* value to write, used when init source is INIT_SRC_INLINE */
__le32 inline_val;
/* number of zeros to write, used when init source is INIT_SRC_ZEROS */
__le32 zeros_count;
/* array offset to write, used when init source is INIT_SRC_ARRAY */
__le32 array_offset;
/* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
struct init_op_array_params runtime;
};
/*
* init operation: write
*/
struct init_write_op {
__le32 data;
/* init operation, from init_op_types enum */
#define INIT_WRITE_OP_OP_MASK 0xF
#define INIT_WRITE_OP_OP_SHIFT 0
/* init source type, taken from init_source_types enum */
#define INIT_WRITE_OP_SOURCE_MASK 0x7
#define INIT_WRITE_OP_SOURCE_SHIFT 4
#define INIT_WRITE_OP_RESERVED_MASK 0x1
#define INIT_WRITE_OP_RESERVED_SHIFT 7
/* indicates if the register is wide-bus */
#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
/* internal (absolute) GRC address, in dwords */
#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
#define INIT_WRITE_OP_ADDRESS_SHIFT 9
union init_write_args args /* Write init operation arguments */;
};
/*
* init operation: read
*/
struct init_read_op {
__le32 op_data;
/* init operation, from init_op_types enum */
#define INIT_READ_OP_OP_MASK 0xF
#define INIT_READ_OP_OP_SHIFT 0
/* polling type, from init_poll_types enum */
#define INIT_READ_OP_POLL_TYPE_MASK 0xF
#define INIT_READ_OP_POLL_TYPE_SHIFT 4
#define INIT_READ_OP_RESERVED_MASK 0x1
#define INIT_READ_OP_RESERVED_SHIFT 8
/* internal (absolute) GRC address, in dwords */
#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
#define INIT_READ_OP_ADDRESS_SHIFT 9
/* expected polling value, used only when polling is done */
__le32 expected_val;
};
/*
* Init operations union
*/
union init_op {
struct init_raw_op raw /* raw init operation */;
struct init_write_op write /* write init operation */;
struct init_read_op read /* read init operation */;
struct init_if_mode_op if_mode /* if_mode init operation */;
struct init_if_phase_op if_phase /* if_phase init operation */;
struct init_callback_op callback /* callback init operation */;
struct init_delay_op delay /* delay init operation */;
};
/*
* Init command operation types
*/
enum init_op_types {
INIT_OP_READ /* GRC read init command */,
INIT_OP_WRITE /* GRC write init command */,
/* Skip init commands if the init modes expression doesn't match */
INIT_OP_IF_MODE,
/* Skip init commands if the init phase doesn't match */
INIT_OP_IF_PHASE,
INIT_OP_DELAY /* delay init command */,
INIT_OP_CALLBACK /* callback init command */,
MAX_INIT_OP_TYPES
};
/*
* init polling types
*/
enum init_poll_types {
INIT_POLL_NONE /* No polling */,
INIT_POLL_EQ /* init value is included in the init command */,
INIT_POLL_OR /* init value is all zeros */,
INIT_POLL_AND /* init value is an array of values */,
MAX_INIT_POLL_TYPES
};
/*
* init source types
*/
enum init_source_types {
INIT_SRC_INLINE /* init value is included in the init command */,
INIT_SRC_ZEROS /* init value is all zeros */,
INIT_SRC_ARRAY /* init value is an array of values */,
INIT_SRC_RUNTIME /* init value is provided during runtime */,
MAX_INIT_SOURCE_TYPES
};
/*
* Internal RAM Offsets macro data
*/
struct iro {
__le32 base /* RAM field offset */;
__le16 m1 /* multiplier 1 */;
__le16 m2 /* multiplier 2 */;
__le16 m3 /* multiplier 3 */;
__le16 size /* RAM field size */;
};
#endif /* __ECORE_HSI_INIT_TOOL__ */

1081
drivers/net/qede/base/ecore_hsi_tools.h
View File

File diff suppressed because it is too large Load Diff

67
drivers/net/qede/base/ecore_init_fw_funcs.c
View File

@ -12,7 +12,8 @@
#include "reg_addr.h"
#include "ecore_rt_defs.h"
#include "ecore_hsi_common.h"
#include "ecore_hsi_tools.h"
#include "ecore_hsi_init_func.h"
#include "ecore_hsi_init_tool.h"
#include "ecore_init_fw_funcs.h"
/* @DPDK CmInterfaceEnum */
@ -187,7 +188,7 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
u8 tc, voq, port_id;
u8 tc, voq, port_id, num_tcs_in_port;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
/* clear PBF lines for all VOQs */
for (voq = 0; voq < MAX_NUM_VOQS; voq++)
@ -201,18 +202,22 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
if (eagle_workaround)
phys_lines -= PBF_CMDQ_EAGLE_WORKAROUND_LINES;
/* find #lines per active physical TC */
phys_lines_per_tc =
phys_lines /
port_params[port_id].num_active_phys_tcs;
num_tcs_in_port = 0;
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) == 1)
num_tcs_in_port++;
}
phys_lines_per_tc = phys_lines / num_tcs_in_port;
/* init registers per active TC */
for (tc = 0;
tc < port_params[port_id].num_active_phys_tcs;
tc++) {
voq =
PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
phys_lines_per_tc);
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) == 1) {
voq = PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
ecore_cmdq_lines_voq_rt_init(p_hwfn,
voq, phys_lines_per_tc);
}
}
/* init registers for pure LB TC */
ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
@ -255,7 +260,7 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
u8 tc, voq, port_id;
u8 tc, voq, port_id, num_tcs_in_port;
u32 usable_blocks, pure_lb_blocks, phys_blocks;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
@ -266,9 +271,15 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
BTB_HEADROOM_BLOCKS;
if (eagle_workaround)
usable_blocks -= BTB_EAGLE_WORKAROUND_BLOCKS;
num_tcs_in_port = 0;
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) == 1)
num_tcs_in_port++;
pure_lb_blocks =
(usable_blocks * BTB_PURE_LB_FACTOR) /
(port_params[port_id].num_active_phys_tcs *
(num_tcs_in_port *
BTB_PURE_LB_FACTOR + BTB_PURE_LB_RATIO);
pure_lb_blocks =
OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS,
@ -276,17 +287,19 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
phys_blocks =
(usable_blocks -
pure_lb_blocks) /
port_params[port_id].num_active_phys_tcs;
num_tcs_in_port;
/* init physical TCs */
for (tc = 0;
tc < port_params[port_id].num_active_phys_tcs;
tc < NUM_OF_PHYS_TCS;
tc++) {
voq =
PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
STORE_RT_REG(p_hwfn,
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) == 1) {
voq = PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(voq),
phys_blocks);
}
}
/* init pure LB TC */
STORE_RT_REG(p_hwfn,
@ -610,18 +623,6 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
(QM_OPPOR_PQ_EMPTY_DEF <<
QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
/* check eagle workaround */
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
if (port_params[port_id].active &&
port_params[port_id].num_active_phys_tcs >
EAGLE_WORKAROUND_TC &&
ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
DP_NOTICE(p_hwfn, true,
"Can't config 8 TCs with Eagle"
" eng1 workaround");
return -1;
}
}
/* enable/disable PF RL */
ecore_enable_pf_rl(p_hwfn, pf_rl_en);
/* enable/disable PF WFQ */

2
drivers/net/qede/base/ecore_init_ops.c
View File

@ -575,7 +575,7 @@ enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
offset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;
offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
offset = buf_hdr[BIN_BUF_INIT_CMD].offset;

139
drivers/net/qede/base/ecore_int.c
View File

@ -284,16 +284,7 @@ static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
#define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
{
u32 tmp, reg_addr;
reg_addr =
attn_blocks[BLOCK_PGLUE_B].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
int_regs[0]->mask_addr;
/* Mask unnecessary attentions -@TBD move to MFW */
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
tmp |= (1 << 19); /* Was PGL_PCIE_ATTN */
ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
u32 tmp;
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
PGLUE_B_REG_TX_ERR_WR_DETAILS2);
@ -407,32 +398,6 @@ static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
return ECORE_SUCCESS;
}
static enum _ecore_status_t ecore_nig_attn_cb(struct ecore_hwfn *p_hwfn)
{
u32 tmp, reg_addr;
/* Mask unnecessary attentions -@TBD move to MFW */
reg_addr =
attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
int_regs[3]->mask_addr;
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
tmp |= (1 << 0); /* Was 3_P0_TX_PAUSE_TOO_LONG_INT */
tmp |= NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT;
ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
reg_addr =
attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
int_regs[5]->mask_addr;
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
tmp |= (1 << 0); /* Was 5_P1_TX_PAUSE_TOO_LONG_INT */
ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
/* TODO - a bit risky to return success here; But alternative is to
* actually read the multitdue of interrupt register of the block.
*/
return ECORE_SUCCESS;
}
static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
{
DP_NOTICE(p_hwfn, false, "FW assertion!\n");
@ -559,7 +524,7 @@ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
{"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
{"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
MAX_BLOCK_ID},
{"NIG", ATTENTION_PAR_INT, ecore_nig_attn_cb, BLOCK_NIG},
{"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
{"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
{"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
{"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
@ -839,43 +804,10 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
rc = p_aeu->cb(p_hwfn);
}
/* Handle HW block interrupt registers */
if (p_aeu->block_index != MAX_BLOCK_ID) {
u16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);
struct attn_hw_block *p_block;
int i;
p_block = &attn_blocks[p_aeu->block_index];
/* Handle each interrupt register */
for (i = 0;
i < p_block->chip_regs[chip_type].num_of_int_regs; i++) {
struct attn_hw_reg *p_reg_desc;
u32 sts_addr;
p_reg_desc = p_block->chip_regs[chip_type].int_regs[i];
/* In case of fatal attention, don't clear the status
* so it would appear in idle check.
*/
if (rc == ECORE_SUCCESS)
sts_addr = p_reg_desc->sts_clr_addr;
else
sts_addr = p_reg_desc->sts_addr;
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);
mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
p_reg_desc->mask_addr);
ecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,
p_block,
ECORE_ATTN_TYPE_ATTN,
val, mask);
#ifndef REMOVE_DBG
interrupts[i] = val;
#endif
}
}
/* Print HW block interrupt registers */
if (p_aeu->block_index != MAX_BLOCK_ID)
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
p_aeu->block_index, ATTN_TYPE_INTERRUPT);
/* Reach assertion if attention is fatal */
if (rc != ECORE_SUCCESS) {
@ -905,33 +837,6 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
return rc;
}
static void ecore_int_parity_print(struct ecore_hwfn *p_hwfn,
struct aeu_invert_reg_bit *p_aeu,
struct attn_hw_block *p_block, u8 bit_index)
{
u16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);
int i;
for (i = 0; i < p_block->chip_regs[chip_type].num_of_prty_regs; i++) {
struct attn_hw_reg *p_reg_desc;
u32 val, mask;
p_reg_desc = p_block->chip_regs[chip_type].prty_regs[i];
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
p_reg_desc->sts_clr_addr);
mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
p_reg_desc->mask_addr);
DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
"%s[%d] - parity register[%d] is %08x [mask is %08x]\n",
p_aeu->bit_name, bit_index, i, val, mask);
ecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,
p_block,
ECORE_ATTN_TYPE_PARITY,
val, mask);
}
}
/**
* @brief ecore_int_deassertion_parity - handle a single parity AEU source
*
@ -949,19 +854,15 @@ static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
p_aeu->bit_name, bit_index);
if (block_id != MAX_BLOCK_ID) {
ecore_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],
bit_index);
if (block_id != MAX_BLOCK_ID)
return;
/* In A0, there's a single parity bit for several blocks */
if (block_id == BLOCK_BTB) {
ecore_int_parity_print(p_hwfn, p_aeu,
&attn_blocks[BLOCK_OPTE],
bit_index);
ecore_int_parity_print(p_hwfn, p_aeu,
&attn_blocks[BLOCK_MCP],
bit_index);
}
/* In A0, there's a single parity bit for several blocks */
if (block_id == BLOCK_BTB) {
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
BLOCK_OPTE, ATTN_TYPE_PARITY);
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
BLOCK_MCP, ATTN_TYPE_PARITY);
}
}
@ -1778,7 +1679,7 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
enum ecore_int_mode int_mode)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 tmp, reg_addr;
u32 tmp;
/* @@@tmp - Mask General HW attentions 0-31, Enable 32-36 */
tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
@ -1794,16 +1695,6 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
tmp &= ~0x800;
ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
/* @@@tmp - Mask interrupt sources - should move to init tool;
* Also, correct for A0 [might still change in B0.
*/
reg_addr =
attn_blocks[BLOCK_BRB].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
int_regs[0]->mask_addr;
tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
tmp |= (1 << 21); /* Was PKT4_LEN_ERROR */
ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
ecore_int_igu_enable_attn(p_hwfn, p_ptt);
if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {