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net/mlx5: create advanced Rx object via DevX

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Implement function mlx5_devx_cmd_create_tir() to create TIR
object using DevX API..
Add related structs in mlx5.h and mlx5_prm.h.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit is contained in:
Dekel Peled 2019-07-22 14:52:08 +00:00 committed by Ferruh Yigit
parent 5bf204fef1
commit c3aea272ee
3 changed files with 179 additions and 0 deletions
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26
drivers/net/mlx5/mlx5.h
View File

@ -320,6 +320,30 @@ struct mlx5_devx_modify_rq_attr {
uint32_t lwm:16; /* Contained WQ lwm. */
};
struct mlx5_rx_hash_field_select {
uint32_t l3_prot_type:1;
uint32_t l4_prot_type:1;
uint32_t selected_fields:30;
};
/* TIR attributes structure, used by TIR operations. */
struct mlx5_devx_tir_attr {
uint32_t disp_type:4;
uint32_t lro_timeout_period_usecs:16;
uint32_t lro_enable_mask:4;
uint32_t lro_max_msg_sz:8;
uint32_t inline_rqn:24;
uint32_t rx_hash_symmetric:1;
uint32_t tunneled_offload_en:1;
uint32_t indirect_table:24;
uint32_t rx_hash_fn:4;
uint32_t self_lb_block:2;
uint32_t transport_domain:24;
uint32_t rx_hash_toeplitz_key[10];
struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
};
/**
* Type of object being allocated.
*/
@ -805,5 +829,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
int socket);
int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
struct mlx5_devx_modify_rq_attr *rq_attr);
struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
struct mlx5_devx_tir_attr *tir_attr);
#endif /* RTE_PMD_MLX5_H_ */

72
drivers/net/mlx5/mlx5_devx_cmds.c
View File

@ -576,3 +576,75 @@ mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
}
return ret;
}
/**
* Create TIR using DevX API.
*
* @param[in] ctx
* ibv_context returned from mlx5dv_open_device.
* @param [in] tir_attr
* Pointer to TIR attributes structure.
*
* @return
* The DevX object created, NULL otherwise and rte_errno is set.
*/
struct mlx5_devx_obj *
mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
struct mlx5_devx_tir_attr *tir_attr)
{
uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
void *tir_ctx, *outer, *inner;
struct mlx5_devx_obj *tir = NULL;
int i;
tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
if (!tir) {
DRV_LOG(ERR, "Failed to allocate TIR data");
rte_errno = ENOMEM;
return NULL;
}
MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
tir_attr->lro_timeout_period_usecs);
MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
tir_attr->tunneled_offload_en);
MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
for (i = 0; i < 10; i++) {
MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
tir_attr->rx_hash_toeplitz_key[i]);
}
outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
tir_attr->rx_hash_field_selector_outer.l3_prot_type);
MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
tir_attr->rx_hash_field_selector_outer.l4_prot_type);
MLX5_SET(rx_hash_field_select, outer, selected_fields,
tir_attr->rx_hash_field_selector_outer.selected_fields);
inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
tir_attr->rx_hash_field_selector_inner.l3_prot_type);
MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
tir_attr->rx_hash_field_selector_inner.l4_prot_type);
MLX5_SET(rx_hash_field_select, inner, selected_fields,
tir_attr->rx_hash_field_selector_inner.selected_fields);
tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
out, sizeof(out));
if (!tir->obj) {
DRV_LOG(ERR, "Failed to create TIR using DevX");
rte_errno = errno;
rte_free(tir);
return NULL;
}
tir->id = MLX5_GET(create_tir_out, out, tirn);
return tir;
}

81
drivers/net/mlx5/mlx5_prm.h
View File

@ -627,6 +627,7 @@ enum {
MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
MLX5_CMD_OP_CREATE_MKEY = 0x200,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
MLX5_CMD_OP_QUERY_TIS = 0x915,
@ -1407,6 +1408,86 @@ struct mlx5_ifc_modify_rq_in_bits {
struct mlx5_ifc_rqc_bits ctx;
};
enum {
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
};
struct mlx5_ifc_rx_hash_field_select_bits {
u8 l3_prot_type[0x1];
u8 l4_prot_type[0x1];
u8 selected_fields[0x1e];
};
enum {
MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
};
enum {
MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
};
enum {
MLX5_RX_HASH_FN_NONE = 0x0,
MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
};
enum {
MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
};
struct mlx5_ifc_tirc_bits {
u8 reserved_at_0[0x20];
u8 disp_type[0x4];
u8 reserved_at_24[0x1c];
u8 reserved_at_40[0x40];
u8 reserved_at_80[0x4];
u8 lro_timeout_period_usecs[0x10];
u8 lro_enable_mask[0x4];
u8 lro_max_msg_sz[0x8];
u8 reserved_at_a0[0x40];
u8 reserved_at_e0[0x8];
u8 inline_rqn[0x18];
u8 rx_hash_symmetric[0x1];
u8 reserved_at_101[0x1];
u8 tunneled_offload_en[0x1];
u8 reserved_at_103[0x5];
u8 indirect_table[0x18];
u8 rx_hash_fn[0x4];
u8 reserved_at_124[0x2];
u8 self_lb_block[0x2];
u8 transport_domain[0x18];
u8 rx_hash_toeplitz_key[10][0x20];
struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
u8 reserved_at_2c0[0x4c0];
};
struct mlx5_ifc_create_tir_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x8];
u8 tirn[0x18];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_create_tir_in_bits {
u8 opcode[0x10];
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0xc0];
struct mlx5_ifc_tirc_bits ctx;
};
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc