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bus/dpaa: add QMAN driver core routines

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Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
This commit is contained in:
Shreyansh Jain 2017-09-28 17:59:31 +05:30 committed by Ferruh Yigit
parent f6fadc3e63
commit c47ff048b9
8 changed files with 4149 additions and 0 deletions
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1
config/defconfig_arm64-dpaa-linuxapp-gcc
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@ -49,3 +49,4 @@ CONFIG_RTE_PKTMBUF_HEADROOM=128
# NXP DPAA Bus
CONFIG_RTE_LIBRTE_DPAA_BUS=y
CONFIG_RTE_LIBRTE_DPAA_DEBUG_DRIVER=n
CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n

2
drivers/bus/dpaa/Makefile
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@ -63,7 +63,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \
base/fman/of.c \
base/fman/netcfg_layer.c \
base/qbman/process.c \
base/qbman/qman.c \
base/qbman/qman_driver.c \
base/qbman/dpaa_alloc.c \
base/qbman/dpaa_sys.c
# Link Pthread

88
drivers/bus/dpaa/base/qbman/dpaa_alloc.c Normal file
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@ -0,0 +1,88 @@
/*-
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* BSD LICENSE
*
* Copyright 2009-2016 Freescale Semiconductor Inc.
* Copyright 2017 NXP.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the above-listed copyright holders nor the
* names of any contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* GPL LICENSE SUMMARY
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "dpaa_sys.h"
#include <process.h>
#include <fsl_qman.h>
int qman_alloc_fqid_range(u32 *result, u32 count, u32 align, int partial)
{
return process_alloc(dpaa_id_fqid, result, count, align, partial);
}
void qman_release_fqid_range(u32 fqid, u32 count)
{
process_release(dpaa_id_fqid, fqid, count);
}
int qman_reserve_fqid_range(u32 fqid, unsigned int count)
{
return process_reserve(dpaa_id_fqid, fqid, count);
}
int qman_alloc_pool_range(u32 *result, u32 count, u32 align, int partial)
{
return process_alloc(dpaa_id_qpool, result, count, align, partial);
}
void qman_release_pool_range(u32 pool, u32 count)
{
process_release(dpaa_id_qpool, pool, count);
}
int qman_reserve_pool_range(u32 pool, u32 count)
{
return process_reserve(dpaa_id_qpool, pool, count);
}
int qman_alloc_cgrid_range(u32 *result, u32 count, u32 align, int partial)
{
return process_alloc(dpaa_id_cgrid, result, count, align, partial);
}
void qman_release_cgrid_range(u32 cgrid, u32 count)
{
process_release(dpaa_id_cgrid, cgrid, count);
}
int qman_reserve_cgrid_range(u32 cgrid, u32 count)
{
return process_reserve(dpaa_id_cgrid, cgrid, count);
}

2402
drivers/bus/dpaa/base/qbman/qman.c Normal file
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888
drivers/bus/dpaa/base/qbman/qman.h Normal file
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@ -0,0 +1,888 @@
/*-
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* BSD LICENSE
*
* Copyright 2008-2016 Freescale Semiconductor Inc.
* Copyright 2017 NXP.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the above-listed copyright holders nor the
* names of any contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* GPL LICENSE SUMMARY
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_priv.h"
/***************************/
/* Portal register assists */
/***************************/
#define QM_REG_EQCR_PI_CINH 0x3000
#define QM_REG_EQCR_CI_CINH 0x3040
#define QM_REG_EQCR_ITR 0x3080
#define QM_REG_DQRR_PI_CINH 0x3100
#define QM_REG_DQRR_CI_CINH 0x3140
#define QM_REG_DQRR_ITR 0x3180
#define QM_REG_DQRR_DCAP 0x31C0
#define QM_REG_DQRR_SDQCR 0x3200
#define QM_REG_DQRR_VDQCR 0x3240
#define QM_REG_DQRR_PDQCR 0x3280
#define QM_REG_MR_PI_CINH 0x3300
#define QM_REG_MR_CI_CINH 0x3340
#define QM_REG_MR_ITR 0x3380
#define QM_REG_CFG 0x3500
#define QM_REG_ISR 0x3600
#define QM_REG_IIR 0x36C0
#define QM_REG_ITPR 0x3740
/* Cache-enabled register offsets */
#define QM_CL_EQCR 0x0000
#define QM_CL_DQRR 0x1000
#define QM_CL_MR 0x2000
#define QM_CL_EQCR_PI_CENA 0x3000
#define QM_CL_EQCR_CI_CENA 0x3040
#define QM_CL_DQRR_PI_CENA 0x3100
#define QM_CL_DQRR_CI_CENA 0x3140
#define QM_CL_MR_PI_CENA 0x3300
#define QM_CL_MR_CI_CENA 0x3340
#define QM_CL_CR 0x3800
#define QM_CL_RR0 0x3900
#define QM_CL_RR1 0x3940
/* BTW, the drivers (and h/w programming model) already obtain the required
* synchronisation for portal accesses via lwsync(), hwsync(), and
* data-dependencies. Use of barrier()s or other order-preserving primitives
* simply degrade performance. Hence the use of the __raw_*() interfaces, which
* simply ensure that the compiler treats the portal registers as volatile (ie.
* non-coherent).
*/
/* Cache-inhibited register access. */
#define __qm_in(qm, o) be32_to_cpu(__raw_readl((qm)->ci + (o)))
#define __qm_out(qm, o, val) __raw_writel((cpu_to_be32(val)), \
(qm)->ci + (o))
#define qm_in(reg) __qm_in(&portal->addr, QM_REG_##reg)
#define qm_out(reg, val) __qm_out(&portal->addr, QM_REG_##reg, val)
/* Cache-enabled (index) register access */
#define __qm_cl_touch_ro(qm, o) dcbt_ro((qm)->ce + (o))
#define __qm_cl_touch_rw(qm, o) dcbt_rw((qm)->ce + (o))
#define __qm_cl_in(qm, o) be32_to_cpu(__raw_readl((qm)->ce + (o)))
#define __qm_cl_out(qm, o, val) \
do { \
u32 *__tmpclout = (qm)->ce + (o); \
__raw_writel(cpu_to_be32(val), __tmpclout); \
dcbf(__tmpclout); \
} while (0)
#define __qm_cl_invalidate(qm, o) dccivac((qm)->ce + (o))
#define qm_cl_touch_ro(reg) __qm_cl_touch_ro(&portal->addr, QM_CL_##reg##_CENA)
#define qm_cl_touch_rw(reg) __qm_cl_touch_rw(&portal->addr, QM_CL_##reg##_CENA)
#define qm_cl_in(reg) __qm_cl_in(&portal->addr, QM_CL_##reg##_CENA)
#define qm_cl_out(reg, val) __qm_cl_out(&portal->addr, QM_CL_##reg##_CENA, val)
#define qm_cl_invalidate(reg)\
__qm_cl_invalidate(&portal->addr, QM_CL_##reg##_CENA)
/* Cache-enabled ring access */
#define qm_cl(base, idx) ((void *)base + ((idx) << 6))
/* Cyclic helper for rings. FIXME: once we are able to do fine-grain perf
* analysis, look at using the "extra" bit in the ring index registers to avoid
* cyclic issues.
*/
static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last)
{
/* 'first' is included, 'last' is excluded */
if (first <= last)
return last - first;
return ringsize + last - first;
}
/* Portal modes.
* Enum types;
* pmode == production mode
* cmode == consumption mode,
* dmode == h/w dequeue mode.
* Enum values use 3 letter codes. First letter matches the portal mode,
* remaining two letters indicate;
* ci == cache-inhibited portal register
* ce == cache-enabled portal register
* vb == in-band valid-bit (cache-enabled)
* dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
* As for "enum qm_dqrr_dmode", it should be self-explanatory.
*/
enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
qm_eqcr_pci = 0, /* PI index, cache-inhibited */
qm_eqcr_pce = 1, /* PI index, cache-enabled */
qm_eqcr_pvb = 2 /* valid-bit */
};
enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
qm_dqrr_dpull = 1 /* PDQCR */
};
enum qm_dqrr_pmode { /* s/w-only */
qm_dqrr_pci, /* reads DQRR_PI_CINH */
qm_dqrr_pce, /* reads DQRR_PI_CENA */
qm_dqrr_pvb /* reads valid-bit */
};
enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
qm_dqrr_cci = 0, /* CI index, cache-inhibited */
qm_dqrr_cce = 1, /* CI index, cache-enabled */
qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
};
enum qm_mr_pmode { /* s/w-only */
qm_mr_pci, /* reads MR_PI_CINH */
qm_mr_pce, /* reads MR_PI_CENA */
qm_mr_pvb /* reads valid-bit */
};
enum qm_mr_cmode { /* matches QCSP_CFG::MM */
qm_mr_cci = 0, /* CI index, cache-inhibited */
qm_mr_cce = 1 /* CI index, cache-enabled */
};
/* ------------------------- */
/* --- Portal structures --- */
#define QM_EQCR_SIZE 8
#define QM_DQRR_SIZE 16
#define QM_MR_SIZE 8
struct qm_eqcr {
struct qm_eqcr_entry *ring, *cursor;
u8 ci, available, ithresh, vbit;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
u32 busy;
enum qm_eqcr_pmode pmode;
#endif
};
struct qm_dqrr {
const struct qm_dqrr_entry *ring, *cursor;
u8 pi, ci, fill, ithresh, vbit;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
enum qm_dqrr_dmode dmode;
enum qm_dqrr_pmode pmode;
enum qm_dqrr_cmode cmode;
#endif
};
struct qm_mr {
const struct qm_mr_entry *ring, *cursor;
u8 pi, ci, fill, ithresh, vbit;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
enum qm_mr_pmode pmode;
enum qm_mr_cmode cmode;
#endif
};
struct qm_mc {
struct qm_mc_command *cr;
struct qm_mc_result *rr;
u8 rridx, vbit;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
enum {
/* Can be _mc_start()ed */
qman_mc_idle,
/* Can be _mc_commit()ed or _mc_abort()ed */
qman_mc_user,
/* Can only be _mc_retry()ed */
qman_mc_hw
} state;
#endif
};
#define QM_PORTAL_ALIGNMENT ____cacheline_aligned
struct qm_addr {
void __iomem *ce; /* cache-enabled */
void __iomem *ci; /* cache-inhibited */
};
struct qm_portal {
struct qm_addr addr;
struct qm_eqcr eqcr;
struct qm_dqrr dqrr;
struct qm_mr mr;
struct qm_mc mc;
} QM_PORTAL_ALIGNMENT;
/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
#define EQCR_CARRYCLEAR(p) \
(void *)((unsigned long)(p) & (~(unsigned long)(QM_EQCR_SIZE << 6)))
extern dma_addr_t rte_mem_virt2phy(const void *addr);
/* Bit-wise logic to convert a ring pointer to a ring index */
static inline u8 EQCR_PTR2IDX(struct qm_eqcr_entry *e)
{
return ((uintptr_t)e >> 6) & (QM_EQCR_SIZE - 1);
}
/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
static inline void EQCR_INC(struct qm_eqcr *eqcr)
{
/* NB: this is odd-looking, but experiments show that it generates fast
* code with essentially no branching overheads. We increment to the
* next EQCR pointer and handle overflow and 'vbit'.
*/
struct qm_eqcr_entry *partial = eqcr->cursor + 1;
eqcr->cursor = EQCR_CARRYCLEAR(partial);
if (partial != eqcr->cursor)
eqcr->vbit ^= QM_EQCR_VERB_VBIT;
}
static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
*portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
DPAA_ASSERT(!eqcr->busy);
if (!eqcr->available)
return NULL;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 1;
#endif
return eqcr->cursor;
}
static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
*portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci;
DPAA_ASSERT(!eqcr->busy);
if (!eqcr->available) {
old_ci = eqcr->ci;
eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
eqcr->available += diff;
if (!diff)
return NULL;
}
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 1;
#endif
return eqcr->cursor;
}
static inline void qm_eqcr_abort(struct qm_portal *portal)
{
__maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
DPAA_ASSERT(eqcr->busy);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 0;
#endif
}
static inline struct qm_eqcr_entry *qm_eqcr_pend_and_next(
struct qm_portal *portal, u8 myverb)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
DPAA_ASSERT(eqcr->busy);
DPAA_ASSERT(eqcr->pmode != qm_eqcr_pvb);
if (eqcr->available == 1)
return NULL;
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
dcbf(eqcr->cursor);
EQCR_INC(eqcr);
eqcr->available--;
return eqcr->cursor;
}
#define EQCR_COMMIT_CHECKS(eqcr) \
do { \
DPAA_ASSERT(eqcr->busy); \
DPAA_ASSERT(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff)); \
DPAA_ASSERT(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff)); \
} while (0)
static inline void qm_eqcr_pci_commit(struct qm_portal *portal, u8 myverb)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pci);
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
EQCR_INC(eqcr);
eqcr->available--;
dcbf(eqcr->cursor);
hwsync();
qm_out(EQCR_PI_CINH, EQCR_PTR2IDX(eqcr->cursor));
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 0;
#endif
}
static inline void qm_eqcr_pce_prefetch(struct qm_portal *portal)
{
__maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
qm_cl_invalidate(EQCR_PI);
qm_cl_touch_rw(EQCR_PI);
}
static inline void qm_eqcr_pce_commit(struct qm_portal *portal, u8 myverb)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
EQCR_INC(eqcr);
eqcr->available--;
dcbf(eqcr->cursor);
lwsync();
qm_cl_out(EQCR_PI, EQCR_PTR2IDX(eqcr->cursor));
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 0;
#endif
}
static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
struct qm_eqcr_entry *eqcursor;
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
lwsync();
eqcursor = eqcr->cursor;
eqcursor->__dont_write_directly__verb = myverb | eqcr->vbit;
dcbf(eqcursor);
EQCR_INC(eqcr);
eqcr->available--;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
eqcr->busy = 0;
#endif
}
static inline u8 qm_eqcr_cci_update(struct qm_portal *portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci = eqcr->ci;
eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
eqcr->available += diff;
return diff;
}
static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
{
__maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
qm_cl_touch_ro(EQCR_CI);
}
static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci = eqcr->ci;
eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
qm_cl_invalidate(EQCR_CI);
diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
eqcr->available += diff;
return diff;
}
static inline u8 qm_eqcr_get_ithresh(struct qm_portal *portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
return eqcr->ithresh;
}
static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
eqcr->ithresh = ithresh;
qm_out(EQCR_ITR, ithresh);
}
static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
return eqcr->available;
}
static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
{
register struct qm_eqcr *eqcr = &portal->eqcr;
return QM_EQCR_SIZE - 1 - eqcr->available;
}
#define DQRR_CARRYCLEAR(p) \
(void *)((unsigned long)(p) & (~(unsigned long)(QM_DQRR_SIZE << 6)))
static inline u8 DQRR_PTR2IDX(const struct qm_dqrr_entry *e)
{
return ((uintptr_t)e >> 6) & (QM_DQRR_SIZE - 1);
}
static inline const struct qm_dqrr_entry *DQRR_INC(
const struct qm_dqrr_entry *e)
{
return DQRR_CARRYCLEAR(e + 1);
}
static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
{
qm_out(CFG, (qm_in(CFG) & 0xff0fffff) |
((mf & (QM_DQRR_SIZE - 1)) << 20));
}
static inline const struct qm_dqrr_entry *qm_dqrr_current(
struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
if (!dqrr->fill)
return NULL;
return dqrr->cursor;
}
static inline u8 qm_dqrr_cursor(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
return DQRR_PTR2IDX(dqrr->cursor);
}
static inline u8 qm_dqrr_next(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->fill);
dqrr->cursor = DQRR_INC(dqrr->cursor);
return --dqrr->fill;
}
static inline u8 qm_dqrr_pci_update(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
u8 diff, old_pi = dqrr->pi;
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pci);
dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
dqrr->fill += diff;
return diff;
}
static inline void qm_dqrr_pce_prefetch(struct qm_portal *portal)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
qm_cl_invalidate(DQRR_PI);
qm_cl_touch_ro(DQRR_PI);
}
static inline u8 qm_dqrr_pce_update(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
u8 diff, old_pi = dqrr->pi;
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
dqrr->pi = qm_cl_in(DQRR_PI) & (QM_DQRR_SIZE - 1);
diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
dqrr->fill += diff;
return diff;
}
static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
const struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
/* when accessing 'verb', use __raw_readb() to ensure that compiler
* inlining doesn't try to optimise out "excess reads".
*/
if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
if (!dqrr->pi)
dqrr->vbit ^= QM_DQRR_VERB_VBIT;
dqrr->fill++;
}
}
static inline void qm_dqrr_cci_consume(struct qm_portal *portal, u8 num)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
qm_out(DQRR_CI_CINH, dqrr->ci);
}
static inline void qm_dqrr_cci_consume_to_current(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
qm_out(DQRR_CI_CINH, dqrr->ci);
}
static inline void qm_dqrr_cce_prefetch(struct qm_portal *portal)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
qm_cl_invalidate(DQRR_CI);
qm_cl_touch_rw(DQRR_CI);
}
static inline void qm_dqrr_cce_consume(struct qm_portal *portal, u8 num)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
qm_cl_out(DQRR_CI, dqrr->ci);
}
static inline void qm_dqrr_cce_consume_to_current(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
qm_cl_out(DQRR_CI, dqrr->ci);
}
static inline void qm_dqrr_cdc_consume_1(struct qm_portal *portal, u8 idx,
int park)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
DPAA_ASSERT(idx < QM_DQRR_SIZE);
qm_out(DQRR_DCAP, (0 << 8) | /* S */
((park ? 1 : 0) << 6) | /* PK */
idx); /* DCAP_CI */
}
static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
const struct qm_dqrr_entry *dq,
int park)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
u8 idx = DQRR_PTR2IDX(dq);
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
DPAA_ASSERT(idx < QM_DQRR_SIZE);
qm_out(DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
idx); /* DQRR_DCAP::DCAP_CI */
}
static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u16 bitmask)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
qm_out(DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
((u32)bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
}
static inline u8 qm_dqrr_cdc_cci(struct qm_portal *portal)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
return qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
}
static inline void qm_dqrr_cdc_cce_prefetch(struct qm_portal *portal)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
qm_cl_invalidate(DQRR_CI);
qm_cl_touch_ro(DQRR_CI);
}
static inline u8 qm_dqrr_cdc_cce(struct qm_portal *portal)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
return qm_cl_in(DQRR_CI) & (QM_DQRR_SIZE - 1);
}
static inline u8 qm_dqrr_get_ci(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
return dqrr->ci;
}
static inline void qm_dqrr_park(struct qm_portal *portal, u8 idx)
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
qm_out(DQRR_DCAP, (0 << 8) | /* S */
(1 << 6) | /* PK */
(idx & (QM_DQRR_SIZE - 1))); /* DCAP_CI */
}
static inline void qm_dqrr_park_current(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
qm_out(DQRR_DCAP, (0 << 8) | /* S */
(1 << 6) | /* PK */
DQRR_PTR2IDX(dqrr->cursor)); /* DCAP_CI */
}
static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
{
qm_out(DQRR_SDQCR, sdqcr);
}
static inline u32 qm_dqrr_sdqcr_get(struct qm_portal *portal)
{
return qm_in(DQRR_SDQCR);
}
static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
{
qm_out(DQRR_VDQCR, vdqcr);
}
static inline u32 qm_dqrr_vdqcr_get(struct qm_portal *portal)
{
return qm_in(DQRR_VDQCR);
}
static inline u8 qm_dqrr_get_ithresh(struct qm_portal *portal)
{
register struct qm_dqrr *dqrr = &portal->dqrr;
return dqrr->ithresh;
}
static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
qm_out(DQRR_ITR, ithresh);
}
static inline u8 qm_dqrr_get_maxfill(struct qm_portal *portal)
{
return (qm_in(CFG) & 0x00f00000) >> 20;
}
/* -------------- */
/* --- MR API --- */
#define MR_CARRYCLEAR(p) \
(void *)((unsigned long)(p) & (~(unsigned long)(QM_MR_SIZE << 6)))
static inline u8 MR_PTR2IDX(const struct qm_mr_entry *e)
{
return ((uintptr_t)e >> 6) & (QM_MR_SIZE - 1);
}
static inline const struct qm_mr_entry *MR_INC(const struct qm_mr_entry *e)
{
return MR_CARRYCLEAR(e + 1);
}
static inline void qm_mr_finish(struct qm_portal *portal)
{
register struct qm_mr *mr = &portal->mr;
if (mr->ci != MR_PTR2IDX(mr->cursor))
pr_crit("Ignoring completed MR entries\n");
}
static inline const struct qm_mr_entry *qm_mr_current(struct qm_portal *portal)
{
register struct qm_mr *mr = &portal->mr;
if (!mr->fill)
return NULL;
return mr->cursor;
}
static inline u8 qm_mr_next(struct qm_portal *portal)
{
register struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->fill);
mr->cursor = MR_INC(mr->cursor);
return --mr->fill;
}
static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
{
register struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->cmode == qm_mr_cci);
mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
qm_out(MR_CI_CINH, mr->ci);
}
static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
{
register struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->cmode == qm_mr_cci);
mr->ci = MR_PTR2IDX(mr->cursor);
qm_out(MR_CI_CINH, mr->ci);
}
static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
qm_out(MR_ITR, ithresh);
}
/* ------------------------------ */
/* --- Management command API --- */
static inline int qm_mc_init(struct qm_portal *portal)
{
register struct qm_mc *mc = &portal->mc;
mc->cr = portal->addr.ce + QM_CL_CR;
mc->rr = portal->addr.ce + QM_CL_RR0;
mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &
QM_MCC_VERB_VBIT) ? 0 : 1;
mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
mc->state = qman_mc_idle;
#endif
return 0;
}
static inline void qm_mc_finish(struct qm_portal *portal)
{
__maybe_unused register struct qm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == qman_mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
if (mc->state != qman_mc_idle)
pr_crit("Losing incomplete MC command\n");
#endif
}
static inline struct qm_mc_command *qm_mc_start(struct qm_portal *portal)
{
register struct qm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == qman_mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
mc->state = qman_mc_user;
#endif
dcbz_64(mc->cr);
return mc->cr;
}
static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
{
register struct qm_mc *mc = &portal->mc;
struct qm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == qman_mc_user);
lwsync();
mc->cr->__dont_write_directly__verb = myverb | mc->vbit;
dcbf(mc->cr);
dcbit_ro(rr);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
mc->state = qman_mc_hw;
#endif
}
static inline struct qm_mc_result *qm_mc_result(struct qm_portal *portal)
{
register struct qm_mc *mc = &portal->mc;
struct qm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == qman_mc_hw);
/* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering.
*/
if (!__raw_readb(&rr->verb)) {
dcbit_ro(rr);
return NULL;
}
mc->rridx ^= 1;
mc->vbit ^= QM_MCC_VERB_VBIT;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
mc->state = qman_mc_idle;
#endif
return rr;
}
/* Portal interrupt register API */
static inline void qm_isr_set_iperiod(struct qm_portal *portal, u16 iperiod)
{
qm_out(ITPR, iperiod);
}
static inline u32 __qm_isr_read(struct qm_portal *portal, enum qm_isr_reg n)
{
#if defined(RTE_ARCH_ARM64)
return __qm_in(&portal->addr, QM_REG_ISR + (n << 6));
#else
return __qm_in(&portal->addr, QM_REG_ISR + (n << 2));
#endif
}
static inline void __qm_isr_write(struct qm_portal *portal, enum qm_isr_reg n,
u32 val)
{
#if defined(RTE_ARCH_ARM64)
__qm_out(&portal->addr, QM_REG_ISR + (n << 6), val);
#else
__qm_out(&portal->addr, QM_REG_ISR + (n << 2), val);
#endif
}

12
drivers/bus/dpaa/base/qbman/qman_driver.c
View File

@ -66,6 +66,7 @@ static __thread struct dpaa_ioctl_portal_map map = {
static int fsl_qman_portal_init(uint32_t index, int is_shared)
{
cpu_set_t cpuset;
struct qman_portal *portal;
int loop, ret;
struct dpaa_ioctl_irq_map irq_map;
@ -116,6 +117,14 @@ static int fsl_qman_portal_init(uint32_t index, int is_shared)
pcfg.node = NULL;
pcfg.irq = fd;
portal = qman_create_affine_portal(&pcfg, NULL);
if (!portal) {
pr_err("Qman portal initialisation failed (%d)\n",
pcfg.cpu);
process_portal_unmap(&map.addr);
return -EBUSY;
}
irq_map.type = dpaa_portal_qman;
irq_map.portal_cinh = map.addr.cinh;
process_portal_irq_map(fd, &irq_map);
@ -124,10 +133,13 @@ static int fsl_qman_portal_init(uint32_t index, int is_shared)
static int fsl_qman_portal_finish(void)
{
__maybe_unused const struct qm_portal_config *cfg;
int ret;
process_portal_irq_unmap(fd);
cfg = qman_destroy_affine_portal();
DPAA_BUG_ON(cfg != &pcfg);
ret = process_portal_unmap(&map.addr);
if (ret)
error(0, ret, "process_portal_unmap()");

755
drivers/bus/dpaa/include/fsl_qman.h
View File

@ -1246,6 +1246,761 @@ struct qman_cgr {
struct list_head node;
};
/* Flags to qman_create_fq() */
#define QMAN_FQ_FLAG_NO_ENQUEUE 0x00000001 /* can't enqueue */
#define QMAN_FQ_FLAG_NO_MODIFY 0x00000002 /* can only enqueue */
#define QMAN_FQ_FLAG_TO_DCPORTAL 0x00000004 /* consumed by CAAM/PME/Fman */
#define QMAN_FQ_FLAG_LOCKED 0x00000008 /* multi-core locking */
#define QMAN_FQ_FLAG_AS_IS 0x00000010 /* query h/w state */
#define QMAN_FQ_FLAG_DYNAMIC_FQID 0x00000020 /* (de)allocate fqid */
/* Flags to qman_destroy_fq() */
#define QMAN_FQ_DESTROY_PARKED 0x00000001 /* FQ can be parked or OOS */
/* Flags from qman_fq_state() */
#define QMAN_FQ_STATE_CHANGING 0x80000000 /* 'state' is changing */
#define QMAN_FQ_STATE_NE 0x40000000 /* retired FQ isn't empty */
#define QMAN_FQ_STATE_ORL 0x20000000 /* retired FQ has ORL */
#define QMAN_FQ_STATE_BLOCKOOS 0xe0000000 /* if any are set, no OOS */
#define QMAN_FQ_STATE_CGR_EN 0x10000000 /* CGR enabled */
#define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */
/* Flags to qman_init_fq() */
#define QMAN_INITFQ_FLAG_SCHED 0x00000001 /* schedule rather than park */
#define QMAN_INITFQ_FLAG_LOCAL 0x00000004 /* set dest portal */
/* Flags to qman_enqueue(). NB, the strange numbering is to align with hardware,
* bit-wise. (NB: the PME API is sensitive to these precise numberings too, so
* any change here should be audited in PME.)
*/
#define QMAN_ENQUEUE_FLAG_WATCH_CGR 0x00080000 /* watch congestion state */
#define QMAN_ENQUEUE_FLAG_DCA 0x00008000 /* perform enqueue-DCA */
#define QMAN_ENQUEUE_FLAG_DCA_PARK 0x00004000 /* If DCA, requests park */
#define QMAN_ENQUEUE_FLAG_DCA_PTR(p) /* If DCA, p is DQRR entry */ \
(((u32)(p) << 2) & 0x00000f00)
#define QMAN_ENQUEUE_FLAG_C_GREEN 0x00000000 /* choose one C_*** flag */
#define QMAN_ENQUEUE_FLAG_C_YELLOW 0x00000008
#define QMAN_ENQUEUE_FLAG_C_RED 0x00000010
#define QMAN_ENQUEUE_FLAG_C_OVERRIDE 0x00000018
/* For the ORP-specific qman_enqueue_orp() variant;
* - this flag indicates "Not Last In Sequence", ie. all but the final fragment
* of a frame.
*/
#define QMAN_ENQUEUE_FLAG_NLIS 0x01000000
/* - this flag performs no enqueue but fills in an ORP sequence number that
* would otherwise block it (eg. if a frame has been dropped).
*/
#define QMAN_ENQUEUE_FLAG_HOLE 0x02000000
/* - this flag performs no enqueue but advances NESN to the given sequence
* number.
*/
#define QMAN_ENQUEUE_FLAG_NESN 0x04000000
/* Flags to qman_modify_cgr() */
#define QMAN_CGR_FLAG_USE_INIT 0x00000001
#define QMAN_CGR_MODE_FRAME 0x00000001
/**
* qman_get_portal_index - get portal configuration index
*/
int qman_get_portal_index(void);
/**
* qman_affine_channel - return the channel ID of an portal
* @cpu: the cpu whose affine portal is the subject of the query
*
* If @cpu is -1, the affine portal for the current CPU will be used. It is a
* bug to call this function for any value of @cpu (other than -1) that is not a
* member of the cpu mask.
*/
u16 qman_affine_channel(int cpu);
/**
* qman_set_vdq - Issue a volatile dequeue command
* @fq: Frame Queue on which the volatile dequeue command is issued
* @num: Number of Frames requested for volatile dequeue
*
* This function will issue a volatile dequeue command to the QMAN.
*/
int qman_set_vdq(struct qman_fq *fq, u16 num);
/**
* qman_dequeue - Get the DQRR entry after volatile dequeue command
* @fq: Frame Queue on which the volatile dequeue command is issued
*
* This function will return the DQRR entry after a volatile dequeue command
* is issued. It will keep returning NULL until there is no packet available on
* the DQRR.
*/
struct qm_dqrr_entry *qman_dequeue(struct qman_fq *fq);
/**
* qman_dqrr_consume - Consume the DQRR entriy after volatile dequeue
* @fq: Frame Queue on which the volatile dequeue command is issued
* @dq: DQRR entry to consume. This is the one which is provided by the
* 'qbman_dequeue' command.
*
* This will consume the DQRR enrey and make it available for next volatile
* dequeue.
*/
void qman_dqrr_consume(struct qman_fq *fq,
struct qm_dqrr_entry *dq);
/**
* qman_poll_dqrr - process DQRR (fast-path) entries
* @limit: the maximum number of DQRR entries to process
*
* Use of this function requires that DQRR processing not be interrupt-driven.
* Ie. the value returned by qman_irqsource_get() should not include
* QM_PIRQ_DQRI. If the current CPU is sharing a portal hosted on another CPU,
* this function will return -EINVAL, otherwise the return value is >=0 and
* represents the number of DQRR entries processed.
*/
int qman_poll_dqrr(unsigned int limit);
/**
* qman_poll
*
* Dispatcher logic on a cpu can use this to trigger any maintenance of the
* affine portal. There are two classes of portal processing in question;
* fast-path (which involves demuxing dequeue ring (DQRR) entries and tracking
* enqueue ring (EQCR) consumption), and slow-path (which involves EQCR
* thresholds, congestion state changes, etc). This function does whatever
* processing is not triggered by interrupts.
*
* Note, if DQRR and some slow-path processing are poll-driven (rather than
* interrupt-driven) then this function uses a heuristic to determine how often
* to run slow-path processing - as slow-path processing introduces at least a
* minimum latency each time it is run, whereas fast-path (DQRR) processing is
* close to zero-cost if there is no work to be done.
*/
void qman_poll(void);
/**
* qman_stop_dequeues - Stop h/w dequeuing to the s/w portal
*
* Disables DQRR processing of the portal. This is reference-counted, so
* qman_start_dequeues() must be called as many times as qman_stop_dequeues() to
* truly re-enable dequeuing.
*/
void qman_stop_dequeues(void);
/**
* qman_start_dequeues - (Re)start h/w dequeuing to the s/w portal
*
* Enables DQRR processing of the portal. This is reference-counted, so
* qman_start_dequeues() must be called as many times as qman_stop_dequeues() to
* truly re-enable dequeuing.
*/
void qman_start_dequeues(void);
/**
* qman_static_dequeue_add - Add pool channels to the portal SDQCR
* @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n)
*
* Adds a set of pool channels to the portal's static dequeue command register
* (SDQCR). The requested pools are limited to those the portal has dequeue
* access to.
*/
void qman_static_dequeue_add(u32 pools);
/**
* qman_static_dequeue_del - Remove pool channels from the portal SDQCR
* @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n)
*
* Removes a set of pool channels from the portal's static dequeue command
* register (SDQCR). The requested pools are limited to those the portal has
* dequeue access to.
*/
void qman_static_dequeue_del(u32 pools);
/**
* qman_static_dequeue_get - return the portal's current SDQCR
*
* Returns the portal's current static dequeue command register (SDQCR). The
* entire register is returned, so if only the currently-enabled pool channels
* are desired, mask the return value with QM_SDQCR_CHANNELS_POOL_MASK.
*/
u32 qman_static_dequeue_get(void);
/**
* qman_dca - Perform a Discrete Consumption Acknowledgment
* @dq: the DQRR entry to be consumed
* @park_request: indicates whether the held-active @fq should be parked
*
* Only allowed in DCA-mode portals, for DQRR entries whose handler callback had
* previously returned 'qman_cb_dqrr_defer'. NB, as with the other APIs, this
* does not take a 'portal' argument but implies the core affine portal from the
* cpu that is currently executing the function. For reasons of locking, this
* function must be called from the same CPU as that which processed the DQRR
* entry in the first place.
*/
void qman_dca(struct qm_dqrr_entry *dq, int park_request);
/**
* qman_eqcr_is_empty - Determine if portal's EQCR is empty
*
* For use in situations where a cpu-affine caller needs to determine when all
* enqueues for the local portal have been processed by Qman but can't use the
* QMAN_ENQUEUE_FLAG_WAIT_SYNC flag to do this from the final qman_enqueue().
* The function forces tracking of EQCR consumption (which normally doesn't
* happen until enqueue processing needs to find space to put new enqueue
* commands), and returns zero if the ring still has unprocessed entries,
* non-zero if it is empty.
*/
int qman_eqcr_is_empty(void);
/**
* qman_set_dc_ern - Set the handler for DCP enqueue rejection notifications
* @handler: callback for processing DCP ERNs
* @affine: whether this handler is specific to the locally affine portal
*
* If a hardware block's interface to Qman (ie. its direct-connect portal, or
* DCP) is configured not to receive enqueue rejections, then any enqueues
* through that DCP that are rejected will be sent to a given software portal.
* If @affine is non-zero, then this handler will only be used for DCP ERNs
* received on the portal affine to the current CPU. If multiple CPUs share a
* portal and they all call this function, they will be setting the handler for
* the same portal! If @affine is zero, then this handler will be global to all
* portals handled by this instance of the driver. Only those portals that do
* not have their own affine handler will use the global handler.
*/
void qman_set_dc_ern(qman_cb_dc_ern handler, int affine);
/* FQ management */
/* ------------- */
/**
* qman_create_fq - Allocates a FQ
* @fqid: the index of the FQD to encapsulate, must be "Out of Service"
* @flags: bit-mask of QMAN_FQ_FLAG_*** options
* @fq: memory for storing the 'fq', with callbacks filled in
*
* Creates a frame queue object for the given @fqid, unless the
* QMAN_FQ_FLAG_DYNAMIC_FQID flag is set in @flags, in which case a FQID is
* dynamically allocated (or the function fails if none are available). Once
* created, the caller should not touch the memory at 'fq' except as extended to
* adjacent memory for user-defined fields (see the definition of "struct
* qman_fq" for more info). NO_MODIFY is only intended for enqueuing to
* pre-existing frame-queues that aren't to be otherwise interfered with, it
* prevents all other modifications to the frame queue. The TO_DCPORTAL flag
* causes the driver to honour any contextB modifications requested in the
* qm_init_fq() API, as this indicates the frame queue will be consumed by a
* direct-connect portal (PME, CAAM, or Fman). When frame queues are consumed by
* software portals, the contextB field is controlled by the driver and can't be
* modified by the caller. If the AS_IS flag is specified, management commands
* will be used on portal @p to query state for frame queue @fqid and construct
* a frame queue object based on that, rather than assuming/requiring that it be
* Out of Service.
*/
int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq);
/**
* qman_destroy_fq - Deallocates a FQ
* @fq: the frame queue object to release
* @flags: bit-mask of QMAN_FQ_FREE_*** options
*
* The memory for this frame queue object ('fq' provided in qman_create_fq()) is
* not deallocated but the caller regains ownership, to do with as desired. The
* FQ must be in the 'out-of-service' state unless the QMAN_FQ_FREE_PARKED flag
* is specified, in which case it may also be in the 'parked' state.
*/
void qman_destroy_fq(struct qman_fq *fq, u32 flags);
/**
* qman_fq_fqid - Queries the frame queue ID of a FQ object
* @fq: the frame queue object to query
*/
u32 qman_fq_fqid(struct qman_fq *fq);
/**
* qman_fq_state - Queries the state of a FQ object
* @fq: the frame queue object to query
* @state: pointer to state enum to return the FQ scheduling state
* @flags: pointer to state flags to receive QMAN_FQ_STATE_*** bitmask
*
* Queries the state of the FQ object, without performing any h/w commands.
* This captures the state, as seen by the driver, at the time the function
* executes.
*/
void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, u32 *flags);
/**
* qman_init_fq - Initialises FQ fields, leaves the FQ "parked" or "scheduled"
* @fq: the frame queue object to modify, must be 'parked' or new.
* @flags: bit-mask of QMAN_INITFQ_FLAG_*** options
* @opts: the FQ-modification settings, as defined in the low-level API
*
* The @opts parameter comes from the low-level portal API. Select
* QMAN_INITFQ_FLAG_SCHED in @flags to cause the frame queue to be scheduled
* rather than parked. NB, @opts can be NULL.
*
* Note that some fields and options within @opts may be ignored or overwritten
* by the driver;
* 1. the 'count' and 'fqid' fields are always ignored (this operation only
* affects one frame queue: @fq).
* 2. the QM_INITFQ_WE_CONTEXTB option of the 'we_mask' field and the associated
* 'fqd' structure's 'context_b' field are sometimes overwritten;
* - if @fq was not created with QMAN_FQ_FLAG_TO_DCPORTAL, then context_b is
* initialised to a value used by the driver for demux.
* - if context_b is initialised for demux, so is context_a in case stashing
* is requested (see item 4).
* (So caller control of context_b is only possible for TO_DCPORTAL frame queue
* objects.)
* 3. if @flags contains QMAN_INITFQ_FLAG_LOCAL, the 'fqd' structure's
* 'dest::channel' field will be overwritten to match the portal used to issue
* the command. If the WE_DESTWQ write-enable bit had already been set by the
* caller, the channel workqueue will be left as-is, otherwise the write-enable
* bit is set and the workqueue is set to a default of 4. If the "LOCAL" flag
* isn't set, the destination channel/workqueue fields and the write-enable bit
* are left as-is.
* 4. if the driver overwrites context_a/b for demux, then if
* QM_INITFQ_WE_CONTEXTA is set, the driver will only overwrite
* context_a.address fields and will leave the stashing fields provided by the
* user alone, otherwise it will zero out the context_a.stashing fields.
*/
int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts);
/**
* qman_schedule_fq - Schedules a FQ
* @fq: the frame queue object to schedule, must be 'parked'
*
* Schedules the frame queue, which must be Parked, which takes it to
* Tentatively-Scheduled or Truly-Scheduled depending on its fill-level.
*/
int qman_schedule_fq(struct qman_fq *fq);
/**
* qman_retire_fq - Retires a FQ
* @fq: the frame queue object to retire
* @flags: FQ flags (as per qman_fq_state) if retirement completes immediately
*
* Retires the frame queue. This returns zero if it succeeds immediately, +1 if
* the retirement was started asynchronously, otherwise it returns negative for
* failure. When this function returns zero, @flags is set to indicate whether
* the retired FQ is empty and/or whether it has any ORL fragments (to show up
* as ERNs). Otherwise the corresponding flags will be known when a subsequent
* FQRN message shows up on the portal's message ring.
*
* NB, if the retirement is asynchronous (the FQ was in the Truly Scheduled or
* Active state), the completion will be via the message ring as a FQRN - but
* the corresponding callback may occur before this function returns!! Ie. the
* caller should be prepared to accept the callback as the function is called,
* not only once it has returned.
*/
int qman_retire_fq(struct qman_fq *fq, u32 *flags);
/**
* qman_oos_fq - Puts a FQ "out of service"
* @fq: the frame queue object to be put out-of-service, must be 'retired'
*
* The frame queue must be retired and empty, and if any order restoration list
* was released as ERNs at the time of retirement, they must all be consumed.
*/
int qman_oos_fq(struct qman_fq *fq);
/**
* qman_fq_flow_control - Set the XON/XOFF state of a FQ
* @fq: the frame queue object to be set to XON/XOFF state, must not be 'oos',
* or 'retired' or 'parked' state
* @xon: boolean to set fq in XON or XOFF state
*
* The frame should be in Tentatively Scheduled state or Truly Schedule sate,
* otherwise the IFSI interrupt will be asserted.
*/
int qman_fq_flow_control(struct qman_fq *fq, int xon);
/**
* qman_query_fq - Queries FQD fields (via h/w query command)
* @fq: the frame queue object to be queried
* @fqd: storage for the queried FQD fields
*/
int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
/**
* qman_query_fq_has_pkts - Queries non-programmable FQD fields and returns '1'
* if packets are in the frame queue. If there are no packets on frame
* queue '0' is returned.
* @fq: the frame queue object to be queried
*/
int qman_query_fq_has_pkts(struct qman_fq *fq);
/**
* qman_query_fq_np - Queries non-programmable FQD fields
* @fq: the frame queue object to be queried
* @np: storage for the queried FQD fields
*/
int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np);
/**
* qman_query_wq - Queries work queue lengths
* @query_dedicated: If non-zero, query length of WQs in the channel dedicated
* to this software portal. Otherwise, query length of WQs in a
* channel specified in wq.
* @wq: storage for the queried WQs lengths. Also specified the channel to
* to query if query_dedicated is zero.
*/
int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq);
/**
* qman_volatile_dequeue - Issue a volatile dequeue command
* @fq: the frame queue object to dequeue from
* @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
* @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
*
* Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
* The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
* the VDQCR is already in use, otherwise returns non-zero for failure. If
* QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
* the VDQCR command has finished executing (ie. once the callback for the last
* DQRR entry resulting from the VDQCR command has been called). If not using
* the FINISH flag, completion can be determined either by detecting the
* presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
* in the "stat" field of the "struct qm_dqrr_entry" passed to the FQ's dequeue
* callback, or by waiting for the QMAN_FQ_STATE_VDQCR bit to disappear from the
* "flags" retrieved from qman_fq_state().
*/
int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
/**
* qman_enqueue - Enqueue a frame to a frame queue
* @fq: the frame queue object to enqueue to
* @fd: a descriptor of the frame to be enqueued
* @flags: bit-mask of QMAN_ENQUEUE_FLAG_*** options
*
* Fills an entry in the EQCR of portal @qm to enqueue the frame described by
* @fd. The descriptor details are copied from @fd to the EQCR entry, the 'pid'
* field is ignored. The return value is non-zero on error, such as ring full
* (and FLAG_WAIT not specified), congestion avoidance (FLAG_WATCH_CGR
* specified), etc. If the ring is full and FLAG_WAIT is specified, this
* function will block. If FLAG_INTERRUPT is set, the EQCI bit of the portal
* interrupt will assert when Qman consumes the EQCR entry (subject to "status
* disable", "enable", and "inhibit" registers). If FLAG_DCA is set, Qman will
* perform an implied "discrete consumption acknowledgment" on the dequeue
* ring's (DQRR) entry, at the ring index specified by the FLAG_DCA_IDX(x)
* macro. (As an alternative to issuing explicit DCA actions on DQRR entries,
* this implicit DCA can delay the release of a "held active" frame queue
* corresponding to a DQRR entry until Qman consumes the EQCR entry - providing
* order-preservation semantics in packet-forwarding scenarios.) If FLAG_DCA is
* set, then FLAG_DCA_PARK can also be set to imply that the DQRR consumption
* acknowledgment should "park request" the "held active" frame queue. Ie.
* when the portal eventually releases that frame queue, it will be left in the
* Parked state rather than Tentatively Scheduled or Truly Scheduled. If the
* portal is watching congestion groups, the QMAN_ENQUEUE_FLAG_WATCH_CGR flag
* is requested, and the FQ is a member of a congestion group, then this
* function returns -EAGAIN if the congestion group is currently congested.
* Note, this does not eliminate ERNs, as the async interface means we can be
* sending enqueue commands to an un-congested FQ that becomes congested before
* the enqueue commands are processed, but it does minimise needless thrashing
* of an already busy hardware resource by throttling many of the to-be-dropped
* enqueues "at the source".
*/
int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags);
int qman_enqueue_multi(struct qman_fq *fq,
const struct qm_fd *fd,
int frames_to_send);
typedef int (*qman_cb_precommit) (void *arg);
/**
* qman_enqueue_orp - Enqueue a frame to a frame queue using an ORP
* @fq: the frame queue object to enqueue to
* @fd: a descriptor of the frame to be enqueued
* @flags: bit-mask of QMAN_ENQUEUE_FLAG_*** options
* @orp: the frame queue object used as an order restoration point.
* @orp_seqnum: the sequence number of this frame in the order restoration path
*
* Similar to qman_enqueue(), but with the addition of an Order Restoration
* Point (@orp) and corresponding sequence number (@orp_seqnum) for this
* enqueue operation to employ order restoration. Each frame queue object acts
* as an Order Definition Point (ODP) by providing each frame dequeued from it
* with an incrementing sequence number, this value is generally ignored unless
* that sequence of dequeued frames will need order restoration later. Each
* frame queue object also encapsulates an Order Restoration Point (ORP), which
* is a re-assembly context for re-ordering frames relative to their sequence
* numbers as they are enqueued. The ORP does not have to be within the frame
* queue that receives the enqueued frame, in fact it is usually the frame
* queue from which the frames were originally dequeued. For the purposes of
* order restoration, multiple frames (or "fragments") can be enqueued for a
* single sequence number by setting the QMAN_ENQUEUE_FLAG_NLIS flag for all
* enqueues except the final fragment of a given sequence number. Ordering
* between sequence numbers is guaranteed, even if fragments of different
* sequence numbers are interlaced with one another. Fragments of the same
* sequence number will retain the order in which they are enqueued. If no
* enqueue is to performed, QMAN_ENQUEUE_FLAG_HOLE indicates that the given
* sequence number is to be "skipped" by the ORP logic (eg. if a frame has been
* dropped from a sequence), or QMAN_ENQUEUE_FLAG_NESN indicates that the given
* sequence number should become the ORP's "Next Expected Sequence Number".
*
* Side note: a frame queue object can be used purely as an ORP, without
* carrying any frames at all. Care should be taken not to deallocate a frame
* queue object that is being actively used as an ORP, as a future allocation
* of the frame queue object may start using the internal ORP before the
* previous use has finished.
*/
int qman_enqueue_orp(struct qman_fq *fq, const struct qm_fd *fd, u32 flags,
struct qman_fq *orp, u16 orp_seqnum);
/**
* qman_alloc_fqid_range - Allocate a contiguous range of FQIDs
* @result: is set by the API to the base FQID of the allocated range
* @count: the number of FQIDs required
* @align: required alignment of the allocated range
* @partial: non-zero if the API can return fewer than @count FQIDs
*
* Returns the number of frame queues allocated, or a negative error code. If
* @partial is non zero, the allocation request may return a smaller range of
* FQs than requested (though alignment will be as requested). If @partial is
* zero, the return value will either be 'count' or negative.
*/
int qman_alloc_fqid_range(u32 *result, u32 count, u32 align, int partial);
static inline int qman_alloc_fqid(u32 *result)
{
int ret = qman_alloc_fqid_range(result, 1, 0, 0);
return (ret > 0) ? 0 : ret;
}
/**
* qman_release_fqid_range - Release the specified range of frame queue IDs
* @fqid: the base FQID of the range to deallocate
* @count: the number of FQIDs in the range
*
* This function can also be used to seed the allocator with ranges of FQIDs
* that it can subsequently allocate from.
*/
void qman_release_fqid_range(u32 fqid, unsigned int count);
static inline void qman_release_fqid(u32 fqid)
{
qman_release_fqid_range(fqid, 1);
}
void qman_seed_fqid_range(u32 fqid, unsigned int count);
int qman_shutdown_fq(u32 fqid);
/**
* qman_reserve_fqid_range - Reserve the specified range of frame queue IDs
* @fqid: the base FQID of the range to deallocate
* @count: the number of FQIDs in the range
*/
int qman_reserve_fqid_range(u32 fqid, unsigned int count);
static inline int qman_reserve_fqid(u32 fqid)
{
return qman_reserve_fqid_range(fqid, 1);
}
/* Pool-channel management */
/**
* qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs
* @result: is set by the API to the base pool-channel ID of the allocated range
* @count: the number of pool-channel IDs required
* @align: required alignment of the allocated range
* @partial: non-zero if the API can return fewer than @count
*
* Returns the number of pool-channel IDs allocated, or a negative error code.
* If @partial is non zero, the allocation request may return a smaller range of
* than requested (though alignment will be as requested). If @partial is zero,
* the return value will either be 'count' or negative.
*/
int qman_alloc_pool_range(u32 *result, u32 count, u32 align, int partial);
static inline int qman_alloc_pool(u32 *result)
{
int ret = qman_alloc_pool_range(result, 1, 0, 0);
return (ret > 0) ? 0 : ret;
}
/**
* qman_release_pool_range - Release the specified range of pool-channel IDs
* @id: the base pool-channel ID of the range to deallocate
* @count: the number of pool-channel IDs in the range
*/
void qman_release_pool_range(u32 id, unsigned int count);
static inline void qman_release_pool(u32 id)
{
qman_release_pool_range(id, 1);
}
/**
* qman_reserve_pool_range - Reserve the specified range of pool-channel IDs
* @id: the base pool-channel ID of the range to reserve
* @count: the number of pool-channel IDs in the range
*/
int qman_reserve_pool_range(u32 id, unsigned int count);
static inline int qman_reserve_pool(u32 id)
{
return qman_reserve_pool_range(id, 1);
}
void qman_seed_pool_range(u32 id, unsigned int count);
/* CGR management */
/* -------------- */
/**
* qman_create_cgr - Register a congestion group object
* @cgr: the 'cgr' object, with fields filled in
* @flags: QMAN_CGR_FLAG_* values
* @opts: optional state of CGR settings
*
* Registers this object to receiving congestion entry/exit callbacks on the
* portal affine to the cpu portal on which this API is executed. If opts is
* NULL then only the callback (cgr->cb) function is registered. If @flags
* contains QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset
* any unspecified parameters) will be used rather than a modify hw hardware
* (which only modifies the specified parameters).
*/
int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
struct qm_mcc_initcgr *opts);
/**
* qman_create_cgr_to_dcp - Register a congestion group object to DCP portal
* @cgr: the 'cgr' object, with fields filled in
* @flags: QMAN_CGR_FLAG_* values
* @dcp_portal: the DCP portal to which the cgr object is registered.
* @opts: optional state of CGR settings
*
*/
int qman_create_cgr_to_dcp(struct qman_cgr *cgr, u32 flags, u16 dcp_portal,
struct qm_mcc_initcgr *opts);
/**
* qman_delete_cgr - Deregisters a congestion group object
* @cgr: the 'cgr' object to deregister
*
* "Unplugs" this CGR object from the portal affine to the cpu on which this API
* is executed. This must be excuted on the same affine portal on which it was
* created.
*/
int qman_delete_cgr(struct qman_cgr *cgr);
/**
* qman_modify_cgr - Modify CGR fields
* @cgr: the 'cgr' object to modify
* @flags: QMAN_CGR_FLAG_* values
* @opts: the CGR-modification settings
*
* The @opts parameter comes from the low-level portal API, and can be NULL.
* Note that some fields and options within @opts may be ignored or overwritten
* by the driver, in particular the 'cgrid' field is ignored (this operation
* only affects the given CGR object). If @flags contains
* QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset any
* unspecified parameters) will be used rather than a modify hw hardware (which
* only modifies the specified parameters).
*/
int qman_modify_cgr(struct qman_cgr *cgr, u32 flags,
struct qm_mcc_initcgr *opts);
/**
* qman_query_cgr - Queries CGR fields
* @cgr: the 'cgr' object to query
* @result: storage for the queried congestion group record
*/
int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *result);
/**
* qman_query_congestion - Queries the state of all congestion groups
* @congestion: storage for the queried state of all congestion groups
*/
int qman_query_congestion(struct qm_mcr_querycongestion *congestion);
/**
* qman_alloc_cgrid_range - Allocate a contiguous range of CGR IDs
* @result: is set by the API to the base CGR ID of the allocated range
* @count: the number of CGR IDs required
* @align: required alignment of the allocated range
* @partial: non-zero if the API can return fewer than @count
*
* Returns the number of CGR IDs allocated, or a negative error code.
* If @partial is non zero, the allocation request may return a smaller range of
* than requested (though alignment will be as requested). If @partial is zero,
* the return value will either be 'count' or negative.
*/
int qman_alloc_cgrid_range(u32 *result, u32 count, u32 align, int partial);
static inline int qman_alloc_cgrid(u32 *result)
{
int ret = qman_alloc_cgrid_range(result, 1, 0, 0);
return (ret > 0) ? 0 : ret;
}
/**
* qman_release_cgrid_range - Release the specified range of CGR IDs
* @id: the base CGR ID of the range to deallocate
* @count: the number of CGR IDs in the range
*/
void qman_release_cgrid_range(u32 id, unsigned int count);
static inline void qman_release_cgrid(u32 id)
{
qman_release_cgrid_range(id, 1);
}
/**
* qman_reserve_cgrid_range - Reserve the specified range of CGR ID
* @id: the base CGR ID of the range to reserve
* @count: the number of CGR IDs in the range
*/
int qman_reserve_cgrid_range(u32 id, unsigned int count);
static inline int qman_reserve_cgrid(u32 id)
{
return qman_reserve_cgrid_range(id, 1);
}
void qman_seed_cgrid_range(u32 id, unsigned int count);
/* Helpers */
/* ------- */
/**
* qman_poll_fq_for_init - Check if an FQ has been initialised from OOS
* @fqid: the FQID that will be initialised by other s/w
*
* In many situations, a FQID is provided for communication between s/w
* entities, and whilst the consumer is responsible for initialising and
* scheduling the FQ, the producer(s) generally create a wrapper FQ object using
* and only call qman_enqueue() (no FQ initialisation, scheduling, etc). Ie;
* qman_create_fq(..., QMAN_FQ_FLAG_NO_MODIFY, ...);
* However, data can not be enqueued to the FQ until it is initialised out of
* the OOS state - this function polls for that condition. It is particularly
* useful for users of IPC functions - each endpoint's Rx FQ is the other
* endpoint's Tx FQ, so each side can initialise and schedule their Rx FQ object
* and then use this API on the (NO_MODIFY) Tx FQ object in order to
* synchronise. The function returns zero for success, +1 if the FQ is still in
* the OOS state, or negative if there was an error.
*/
static inline int qman_poll_fq_for_init(struct qman_fq *fq)
{
struct qm_mcr_queryfq_np np;
int err;
err = qman_query_fq_np(fq, &np);
if (err)
return err;
if ((np.state & QM_MCR_NP_STATE_MASK) == QM_MCR_NP_STATE_OOS)
return 1;
return 0;
}
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#define cpu_to_hw_sg(x) (x)
#define hw_sg_to_cpu(x) (x)
#else
#define cpu_to_hw_sg(x) __cpu_to_hw_sg(x)
#define hw_sg_to_cpu(x) __hw_sg_to_cpu(x)
static inline void __cpu_to_hw_sg(struct qm_sg_entry *sgentry)
{
sgentry->opaque = cpu_to_be64(sgentry->opaque);
sgentry->val = cpu_to_be32(sgentry->val);
sgentry->val_off = cpu_to_be16(sgentry->val_off);
}
static inline void __hw_sg_to_cpu(struct qm_sg_entry *sgentry)
{
sgentry->opaque = be64_to_cpu(sgentry->opaque);
sgentry->val = be32_to_cpu(sgentry->val);
sgentry->val_off = be16_to_cpu(sgentry->val_off);
}
#endif
#ifdef __cplusplus
}

1
drivers/bus/dpaa/include/fsl_usd.h
View File

@ -42,6 +42,7 @@
#define __FSL_USD_H
#include <compat.h>
#include <fsl_qman.h>
#ifdef __cplusplus
extern "C" {