net/liquidio: add API to configure device
Add API to configure device and initialize ethernet device operations. Signed-off-by: Shijith Thotton <shijith.thotton@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Venkat Koppula <venkat.koppula@caviumnetworks.com> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com> Signed-off-by: Mallesham Jatharakonda <mjatharakonda@oneconvergence.com>
This commit is contained in:
Shijith Thotton
Ferruh Yigit
parent
64af21f803
commit
c6186279df
@ -95,6 +95,8 @@ enum lio_card_type {
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#define LIO_BASE_MINOR_VERSION 5
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#define LIO_BASE_MICRO_VERSION 1
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#define LIO_FW_VERSION_LENGTH 32
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/** Tag types used by Octeon cores in its work. */
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enum octeon_tag_type {
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OCTEON_ORDERED_TAG = 0,
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@ -104,6 +106,18 @@ enum octeon_tag_type {
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/* pre-defined host->NIC tag values */
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#define LIO_CONTROL (0x11111110)
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/* used for NIC operations */
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#define LIO_OPCODE 1
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/** LIO_OPCODE subcodes */
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/* This subcode is sent by core PCI driver to indicate cores are ready. */
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#define LIO_OPCODE_IF_CFG 0x09
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/* Interface flags communicated between host driver and core app. */
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enum lio_ifflags {
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LIO_IFFLAG_UNICAST = 0x10
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};
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/* Routines for reading and writing CSRs */
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#ifdef RTE_LIBRTE_LIO_DEBUG_REGS
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#define lio_write_csr(lio_dev, reg_off, value) \
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@ -41,6 +41,166 @@
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#include "lio_ethdev.h"
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#include "lio_rxtx.h"
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static uint64_t
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lio_hweight64(uint64_t w)
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{
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uint64_t res = w - ((w >> 1) & 0x5555555555555555ul);
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res =
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(res & 0x3333333333333333ul) + ((res >> 2) & 0x3333333333333333ul);
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res = (res + (res >> 4)) & 0x0F0F0F0F0F0F0F0Ful;
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res = res + (res >> 8);
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res = res + (res >> 16);
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return (res + (res >> 32)) & 0x00000000000000FFul;
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}
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static int lio_dev_configure(struct rte_eth_dev *eth_dev)
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{
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struct lio_device *lio_dev = LIO_DEV(eth_dev);
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uint16_t timeout = LIO_MAX_CMD_TIMEOUT;
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int retval, num_iqueues, num_oqueues;
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uint8_t mac[ETHER_ADDR_LEN], i;
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struct lio_if_cfg_resp *resp;
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struct lio_soft_command *sc;
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union lio_if_cfg if_cfg;
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uint32_t resp_size;
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PMD_INIT_FUNC_TRACE();
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/* Re-configuring firmware not supported.
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* Can't change tx/rx queues per port from initial value.
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*/
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if (lio_dev->port_configured) {
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if ((lio_dev->nb_rx_queues != eth_dev->data->nb_rx_queues) ||
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(lio_dev->nb_tx_queues != eth_dev->data->nb_tx_queues)) {
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lio_dev_err(lio_dev,
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"rxq/txq re-conf not supported. Restart application with new value.\n");
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return -ENOTSUP;
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}
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return 0;
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}
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lio_dev->nb_rx_queues = eth_dev->data->nb_rx_queues;
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lio_dev->nb_tx_queues = eth_dev->data->nb_tx_queues;
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resp_size = sizeof(struct lio_if_cfg_resp);
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sc = lio_alloc_soft_command(lio_dev, 0, resp_size, 0);
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if (sc == NULL)
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return -ENOMEM;
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resp = (struct lio_if_cfg_resp *)sc->virtrptr;
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/* Firmware doesn't have capability to reconfigure the queues,
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* Claim all queues, and use as many required
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*/
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if_cfg.if_cfg64 = 0;
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if_cfg.s.num_iqueues = lio_dev->nb_tx_queues;
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if_cfg.s.num_oqueues = lio_dev->nb_rx_queues;
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if_cfg.s.base_queue = 0;
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if_cfg.s.gmx_port_id = lio_dev->pf_num;
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lio_prepare_soft_command(lio_dev, sc, LIO_OPCODE,
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LIO_OPCODE_IF_CFG, 0,
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if_cfg.if_cfg64, 0);
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/* Setting wait time in seconds */
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sc->wait_time = LIO_MAX_CMD_TIMEOUT / 1000;
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retval = lio_send_soft_command(lio_dev, sc);
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if (retval == LIO_IQ_SEND_FAILED) {
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lio_dev_err(lio_dev, "iq/oq config failed status: %x\n",
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retval);
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/* Soft instr is freed by driver in case of failure. */
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goto nic_config_fail;
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}
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/* Sleep on a wait queue till the cond flag indicates that the
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* response arrived or timed-out.
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*/
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while ((*sc->status_word == LIO_COMPLETION_WORD_INIT) && --timeout) {
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lio_process_ordered_list(lio_dev);
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rte_delay_ms(1);
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}
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retval = resp->status;
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if (retval) {
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lio_dev_err(lio_dev, "iq/oq config failed\n");
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goto nic_config_fail;
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}
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lio_swap_8B_data((uint64_t *)(&resp->cfg_info),
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sizeof(struct octeon_if_cfg_info) >> 3);
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num_iqueues = lio_hweight64(resp->cfg_info.iqmask);
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num_oqueues = lio_hweight64(resp->cfg_info.oqmask);
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if (!(num_iqueues) || !(num_oqueues)) {
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lio_dev_err(lio_dev,
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"Got bad iqueues (%016lx) or oqueues (%016lx) from firmware.\n",
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(unsigned long)resp->cfg_info.iqmask,
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(unsigned long)resp->cfg_info.oqmask);
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goto nic_config_fail;
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}
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lio_dev_dbg(lio_dev,
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"interface %d, iqmask %016lx, oqmask %016lx, numiqueues %d, numoqueues %d\n",
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eth_dev->data->port_id,
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(unsigned long)resp->cfg_info.iqmask,
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(unsigned long)resp->cfg_info.oqmask,
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num_iqueues, num_oqueues);
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lio_dev->linfo.num_rxpciq = num_oqueues;
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lio_dev->linfo.num_txpciq = num_iqueues;
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for (i = 0; i < num_oqueues; i++) {
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lio_dev->linfo.rxpciq[i].rxpciq64 =
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resp->cfg_info.linfo.rxpciq[i].rxpciq64;
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lio_dev_dbg(lio_dev, "index %d OQ %d\n",
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i, lio_dev->linfo.rxpciq[i].s.q_no);
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}
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for (i = 0; i < num_iqueues; i++) {
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lio_dev->linfo.txpciq[i].txpciq64 =
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resp->cfg_info.linfo.txpciq[i].txpciq64;
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lio_dev_dbg(lio_dev, "index %d IQ %d\n",
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i, lio_dev->linfo.txpciq[i].s.q_no);
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}
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lio_dev->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
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lio_dev->linfo.gmxport = resp->cfg_info.linfo.gmxport;
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lio_dev->linfo.link.link_status64 =
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resp->cfg_info.linfo.link.link_status64;
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/* 64-bit swap required on LE machines */
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lio_swap_8B_data(&lio_dev->linfo.hw_addr, 1);
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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mac[i] = *((uint8_t *)(((uint8_t *)&lio_dev->linfo.hw_addr) +
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2 + i));
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/* Copy the permanent MAC address */
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ether_addr_copy((struct ether_addr *)mac, ð_dev->data->mac_addrs[0]);
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lio_dev->port_configured = 1;
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lio_free_soft_command(sc);
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return 0;
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nic_config_fail:
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lio_dev_err(lio_dev, "Failed retval %d\n", retval);
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lio_free_soft_command(sc);
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lio_free_instr_queue0(lio_dev);
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return -ENODEV;
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}
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/* Define our ethernet definitions */
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static const struct eth_dev_ops liovf_eth_dev_ops = {
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.dev_configure = lio_dev_configure,
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};
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static void
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lio_check_pf_hs_response(void *lio_dev)
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{
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@ -215,13 +375,22 @@ lio_eth_dev_init(struct rte_eth_dev *eth_dev)
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return -EINVAL;
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}
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eth_dev->dev_ops = &liovf_eth_dev_ops;
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eth_dev->data->mac_addrs = rte_zmalloc("lio", ETHER_ADDR_LEN, 0);
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if (eth_dev->data->mac_addrs == NULL) {
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lio_dev_err(lio_dev,
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"MAC addresses memory allocation failed\n");
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eth_dev->dev_ops = NULL;
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return -ENOMEM;
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}
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rte_atomic64_set(&lio_dev->status, LIO_DEV_RUNNING);
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rte_wmb();
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lio_dev->port_configured = 0;
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/* Always allow unicast packets */
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lio_dev->ifflags |= LIO_IFFLAG_UNICAST;
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return 0;
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}
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@ -36,5 +36,41 @@
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#include <stdint.h>
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#include "lio_struct.h"
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#define LIO_MAX_CMD_TIMEOUT 10000 /* 10000ms (10s) */
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#define LIO_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
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struct octeon_if_cfg_info {
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uint64_t iqmask; /** mask for IQs enabled for the port */
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uint64_t oqmask; /** mask for OQs enabled for the port */
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struct octeon_link_info linfo; /** initial link information */
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char lio_firmware_version[LIO_FW_VERSION_LENGTH];
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};
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union lio_if_cfg {
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uint64_t if_cfg64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t base_queue : 16;
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uint64_t num_iqueues : 16;
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uint64_t num_oqueues : 16;
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uint64_t gmx_port_id : 8;
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uint64_t vf_id : 8;
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#else
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uint64_t vf_id : 8;
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uint64_t gmx_port_id : 8;
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uint64_t num_oqueues : 16;
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uint64_t num_iqueues : 16;
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uint64_t base_queue : 16;
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#endif
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} s;
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};
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struct lio_if_cfg_resp {
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uint64_t rh;
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struct octeon_if_cfg_info cfg_info;
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uint64_t status;
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};
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#endif /* _LIO_ETHDEV_H_ */
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@ -274,6 +274,75 @@ struct lio_config {
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int def_rx_buf_size;
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};
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/** Status of a RGMII Link on Octeon as seen by core driver. */
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union octeon_link_status {
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uint64_t link_status64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t duplex : 8;
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uint64_t mtu : 16;
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uint64_t speed : 16;
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uint64_t link_up : 1;
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uint64_t autoneg : 1;
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uint64_t if_mode : 5;
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uint64_t pause : 1;
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uint64_t flashing : 1;
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uint64_t reserved : 15;
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#else
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uint64_t reserved : 15;
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uint64_t flashing : 1;
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uint64_t pause : 1;
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uint64_t if_mode : 5;
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uint64_t autoneg : 1;
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uint64_t link_up : 1;
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uint64_t speed : 16;
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uint64_t mtu : 16;
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uint64_t duplex : 8;
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#endif
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} s;
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};
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/** The rxpciq info passed to host from the firmware */
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union octeon_rxpciq {
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uint64_t rxpciq64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t q_no : 8;
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uint64_t reserved : 56;
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#else
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uint64_t reserved : 56;
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uint64_t q_no : 8;
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#endif
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} s;
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};
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/** Information for a OCTEON ethernet interface shared between core & host. */
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struct octeon_link_info {
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union octeon_link_status link;
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uint64_t hw_addr;
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t gmxport : 16;
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uint64_t macaddr_is_admin_assigned : 1;
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uint64_t vlan_is_admin_assigned : 1;
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uint64_t rsvd : 30;
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uint64_t num_txpciq : 8;
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uint64_t num_rxpciq : 8;
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#else
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uint64_t num_rxpciq : 8;
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uint64_t num_txpciq : 8;
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uint64_t rsvd : 30;
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uint64_t vlan_is_admin_assigned : 1;
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uint64_t macaddr_is_admin_assigned : 1;
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uint64_t gmxport : 16;
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#endif
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union octeon_txpciq txpciq[LIO_MAX_IOQS_PER_IF];
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union octeon_rxpciq rxpciq[LIO_MAX_IOQS_PER_IF];
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};
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/* ----------------------- THE LIO DEVICE --------------------------- */
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/** The lio device.
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* Each lio device has this structure to represent all its
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@ -294,6 +363,8 @@ struct lio_device {
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/** The state of this device */
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rte_atomic64_t status;
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struct octeon_link_info linfo;
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uint8_t *hw_addr;
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struct lio_fn_list fn_list;
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@ -324,6 +395,7 @@ struct lio_device {
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struct rte_eth_dev *eth_dev;
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uint64_t ifflags;
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uint8_t max_rx_queues;
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uint8_t max_tx_queues;
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uint8_t nb_rx_queues;
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