raw/octeontx2_dma: update probe function
Probe function enhanced to allocate and initialize PMD private data. Signed-off-by: Satha Rao <skoteshwar@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
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@ -16,6 +16,8 @@
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#include <otx2_common.h>
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#include "otx2_dpi_rawdev.h"
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static const struct rte_pci_id pci_dma_map[] = {
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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@ -31,11 +33,13 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
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struct rte_pci_device *pci_dev)
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{
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char name[RTE_RAWDEV_NAME_MAX_LEN];
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struct dpi_vf_s *dpivf = NULL;
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struct rte_rawdev *rawdev;
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uint16_t vf_id;
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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return DPI_DMA_QUEUE_SUCCESS;
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if (pci_dev->mem_resource[0].addr == NULL) {
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otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
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@ -49,7 +53,8 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
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pci_dev->addr.function);
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/* Allocate device structure */
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rawdev = rte_rawdev_pmd_allocate(name, 0, rte_socket_id());
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rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
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rte_socket_id());
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if (rawdev == NULL) {
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otx2_err("Rawdev allocation failed");
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return -EINVAL;
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@ -58,7 +63,21 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
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rawdev->device = &pci_dev->device;
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rawdev->driver_name = pci_dev->driver->driver.name;
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return 0;
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dpivf = rawdev->dev_private;
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if (dpivf->state != DPI_QUEUE_STOP) {
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otx2_dpi_dbg("Device already started!!!");
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return -ENODEV;
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}
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vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
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(pci_dev->addr.function & 0x7);
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vf_id -= 1;
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dpivf->state = DPI_QUEUE_START;
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dpivf->vf_id = vf_id;
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dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
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dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
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return DPI_DMA_QUEUE_SUCCESS;
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}
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static int
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56
drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
Normal file
56
drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
Normal file
@ -0,0 +1,56 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _DPI_RAWDEV_H_
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#define _DPI_RAWDEV_H_
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#define DPI_QUEUE_OPEN 0x1
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#define DPI_QUEUE_CLOSE 0x2
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/* DPI VF register offsets from VF_BAR0 */
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#define DPI_VDMA_EN (0x0)
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#define DPI_VDMA_REQQ_CTL (0x8)
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#define DPI_VDMA_DBELL (0x10)
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#define DPI_VDMA_SADDR (0x18)
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#define DPI_VDMA_COUNTS (0x20)
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#define DPI_VDMA_NADDR (0x28)
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#define DPI_VDMA_IWBUSY (0x30)
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#define DPI_VDMA_CNT (0x38)
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#define DPI_VF_INT (0x100)
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#define DPI_VF_INT_W1S (0x108)
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#define DPI_VF_INT_ENA_W1C (0x110)
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#define DPI_VF_INT_ENA_W1S (0x118)
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#define DPI_MAX_VFS 8
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#define DPI_DMA_CMD_SIZE 64
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#define DPI_CHUNK_SIZE 1024
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#define DPI_QUEUE_STOP 0x0
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#define DPI_QUEUE_START 0x1
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struct dpi_vf_s {
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struct rte_pci_device *dev;
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uint8_t state;
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uint16_t vf_id;
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uint8_t domain;
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uintptr_t vf_bar0;
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uintptr_t vf_bar2;
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uint16_t pool_size_m1;
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uint16_t index;
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uint64_t *base_ptr;
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void *chunk_pool;
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struct otx2_mbox *mbox;
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};
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struct dpi_rawdev_conf_s {
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void *chunk_pool;
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};
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enum dpi_dma_queue_result_e {
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DPI_DMA_QUEUE_SUCCESS = 0,
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DPI_DMA_QUEUE_NO_MEMORY = -1,
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DPI_DMA_QUEUE_INVALID_PARAM = -2,
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};
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#endif /* _DPI_RAWDEV_H_ */
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