ixgbe/base: flow director changes
Signed-off-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com> [Thomas: split code drop]
This commit is contained in:
Jijiang Liu
Thomas Monjalon
parent
1acad5657a
commit
da7c937efc
@ -1464,8 +1464,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
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* @hw: pointer to hardware structure
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* @fdirctrl: value to write to flow director control register, initially
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* contains just the value of the Rx packet buffer allocation
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* @cloud_mode: true - cloude mode, false - other mode
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**/
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
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bool cloud_mode)
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{
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DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
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@ -1662,34 +1664,20 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
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u32 bucket_hash = 0;
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u32 hi_dword = 0;
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u32 i = 0;
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/* Apply masks to input data */
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input->dword_stream[0] &= input_mask->dword_stream[0];
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input->dword_stream[1] &= input_mask->dword_stream[1];
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input->dword_stream[2] &= input_mask->dword_stream[2];
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input->dword_stream[3] &= input_mask->dword_stream[3];
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input->dword_stream[4] &= input_mask->dword_stream[4];
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input->dword_stream[5] &= input_mask->dword_stream[5];
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input->dword_stream[6] &= input_mask->dword_stream[6];
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input->dword_stream[7] &= input_mask->dword_stream[7];
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input->dword_stream[8] &= input_mask->dword_stream[8];
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input->dword_stream[9] &= input_mask->dword_stream[9];
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input->dword_stream[10] &= input_mask->dword_stream[10];
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for (i = 0; i < 14; i++)
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input->dword_stream[i] &= input_mask->dword_stream[i];
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/* record the flow_vm_vlan bits as they are a key part to the hash */
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flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
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/* generate common hash dword */
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hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
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input->dword_stream[2] ^
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input->dword_stream[3] ^
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input->dword_stream[4] ^
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input->dword_stream[5] ^
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input->dword_stream[6] ^
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input->dword_stream[7] ^
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input->dword_stream[8] ^
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input->dword_stream[9] ^
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input->dword_stream[10]);
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for (i = 1; i <= 13; i++)
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hi_dword ^= input->dword_stream[i];
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hi_hash_dword = IXGBE_NTOHL(hi_dword);
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/* low dword is word swapped version of common */
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lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
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@ -1708,21 +1696,8 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
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/* Process remaining 30 bit of the key */
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IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
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IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
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for (i = 1; i <= 15; i++)
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IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
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/*
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* Limit hash to 13 bits since max bucket count is 8K.
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@ -1769,7 +1744,7 @@ STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
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IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input_mask)
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union ixgbe_atr_input *input_mask, bool cloud_mode)
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{
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/* mask IPv6 since it is currently not supported */
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u32 fdirm = IXGBE_FDIRM_DIPv6;
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@ -1868,7 +1843,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id, u8 queue)
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u16 soft_id, u8 queue, bool cloud_mode)
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{
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u32 fdirport, fdirvlan, fdirhash, fdircmd;
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@ -1917,6 +1892,8 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
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if (queue == IXGBE_FDIR_DROP_QUEUE)
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fdircmd |= IXGBE_FDIRCMD_DROP;
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if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
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fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
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fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
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fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
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fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
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@ -1983,7 +1960,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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union ixgbe_atr_input *input_mask,
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u16 soft_id, u8 queue)
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u16 soft_id, u8 queue, bool cloud_mode)
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{
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s32 err = IXGBE_ERR_CONFIG;
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@ -1995,6 +1972,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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*/
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switch (input->formatted.flow_type) {
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case IXGBE_ATR_FLOW_TYPE_IPV4:
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case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
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input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
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if (input->formatted.dst_port || input->formatted.src_port) {
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DEBUGOUT(" Error on src/dst port\n");
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@ -2002,12 +1980,15 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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}
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break;
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case IXGBE_ATR_FLOW_TYPE_SCTPV4:
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case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
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if (input->formatted.dst_port || input->formatted.src_port) {
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DEBUGOUT(" Error on src/dst port\n");
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return IXGBE_ERR_CONFIG;
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}
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case IXGBE_ATR_FLOW_TYPE_TCPV4:
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case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
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case IXGBE_ATR_FLOW_TYPE_UDPV4:
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case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
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input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
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IXGBE_ATR_L4TYPE_MASK;
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break;
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@ -2017,7 +1998,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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}
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/* program input mask into the HW */
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err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
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err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
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if (err)
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return err;
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@ -2026,7 +2007,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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/* program filters to filter memory */
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return ixgbe_fdir_write_perfect_filter_82599(hw, input,
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soft_id, queue);
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soft_id, queue, cloud_mode);
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}
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/**
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@ -139,16 +139,17 @@ s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
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s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
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s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
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s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
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bool cloud_mode);
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s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common,
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u8 queue);
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input_mask);
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union ixgbe_atr_input *input_mask, bool cloud_mode);
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id, u8 queue);
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u16 soft_id, u8 queue, bool cloud_mode);
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s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id);
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@ -156,7 +157,8 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask,
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u16 soft_id,
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u8 queue);
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u8 queue,
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bool cloud_mode);
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void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask);
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u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
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@ -332,6 +332,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define IXGBE_FDIRSIP4M 0x0EE40
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#define IXGBE_FDIRTCPM 0x0EE44
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#define IXGBE_FDIRUDPM 0x0EE48
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#define IXGBE_FDIRSCTPM 0x0EE78
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#define IXGBE_FDIRIP6M 0x0EE74
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#define IXGBE_FDIRM 0x0EE70
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@ -2340,6 +2341,7 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
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#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
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#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
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#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000
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#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
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#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
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#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
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@ -2394,10 +2396,11 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
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#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
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#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
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#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23
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#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
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#define IXGBE_FDIR_INIT_DONE_POLL 10
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#define IXGBE_FDIRCMD_CMD_POLL 10
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#define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000
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#define IXGBE_FDIR_DROP_QUEUE 127
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#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */
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@ -2686,6 +2689,7 @@ typedef u32 ixgbe_physical_layer;
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#define IXGBE_ATR_L4TYPE_TCP 0x2
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#define IXGBE_ATR_L4TYPE_SCTP 0x3
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#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
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#define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10
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enum ixgbe_atr_flow_type {
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IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
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IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
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@ -2695,6 +2699,14 @@ enum ixgbe_atr_flow_type {
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IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
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IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
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IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16,
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IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17,
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};
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/* Flow Director ATR input struct. */
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@ -2706,6 +2718,9 @@ union ixgbe_atr_input {
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* flow_type - 1 byte
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* vlan_id - 2 bytes
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* src_ip - 16 bytes
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* inner_mac - 6 bytes
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* cloud_mode - 2 bytes
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* tni_vni - 4 bytes
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* dst_ip - 16 bytes
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* src_port - 2 bytes
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* dst_port - 2 bytes
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@ -2718,12 +2733,15 @@ union ixgbe_atr_input {
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__be16 vlan_id;
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__be32 dst_ip[4];
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__be32 src_ip[4];
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u8 inner_mac[6];
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__be16 tunnel_type;
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__be32 tni_vni;
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__be16 src_port;
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__be16 dst_port;
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__be16 flex_bytes;
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__be16 bkt_hash;
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} formatted;
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__be32 dword_stream[11];
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__be32 dword_stream[14];
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};
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/* Flow Director compressed ATR hash input struct */
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@ -280,9 +280,8 @@ ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
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flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
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/* generate common hash dword */
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for (i = 10; i; i -= 2)
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common_hash_dword ^= atr_input->dword_stream[i] ^
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atr_input->dword_stream[i - 1];
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for (i = 1; i <= 13; i++)
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common_hash_dword ^= atr_input->dword_stream[i];
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hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
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