ixgbe/base: fdir cloud mode
Supports flow director cloud mode in IXGBE base code. Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
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@ -1516,6 +1516,9 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
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(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
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(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
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if (cloud_mode)
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fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
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IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
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/* write hashes and fdirctrl register, poll for completion */
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ixgbe_fdir_enable_82599(hw, fdirctrl);
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@ -1785,6 +1788,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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/* mask IPv6 since it is currently not supported */
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u32 fdirm = IXGBE_FDIRM_DIPv6;
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u32 fdirtcpm;
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u32 fdirip6m;
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DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
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/*
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@ -1857,6 +1861,49 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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return IXGBE_ERR_CONFIG;
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}
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if (cloud_mode) {
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fdirm |= IXGBE_FDIRM_L3P;
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fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
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fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
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switch (input_mask->formatted.inner_mac[0] & 0xFF) {
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case 0x00:
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/* Mask inner MAC, fall through */
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fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
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case 0xFF:
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break;
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default:
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DEBUGOUT(" Error on inner_mac byte mask\n");
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return IXGBE_ERR_CONFIG;
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}
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switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
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case 0x0:
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/* Mask vxlan id */
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fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
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break;
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case 0x00FFFFFF:
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fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
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break;
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case 0xFFFFFFFF:
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break;
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default:
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DEBUGOUT(" Error on TNI/VNI byte mask\n");
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return IXGBE_ERR_CONFIG;
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}
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switch (input_mask->formatted.tunnel_type & 0xFFFF) {
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case 0x0:
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/* Mask turnnel type, fall through */
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fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
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case 0xFFFF:
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break;
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default:
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DEBUGOUT(" Error on tunnel type byte mask\n");
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return IXGBE_ERR_CONFIG;
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}
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IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
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}
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/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
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IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
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@ -1882,6 +1929,9 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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u16 soft_id, u8 queue, bool cloud_mode)
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{
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u32 fdirport, fdirvlan, fdirhash, fdircmd;
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u32 addr_low, addr_high;
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u32 cloud_type = 0;
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s32 err;
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DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
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@ -1911,6 +1961,21 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
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IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
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if (cloud_mode) {
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if (input->formatted.tunnel_type != 0)
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cloud_type = 0x80000000;
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addr_low = ((u32)input->formatted.inner_mac[0] |
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((u32)input->formatted.inner_mac[1] << 8) |
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((u32)input->formatted.inner_mac[2] << 16) |
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((u32)input->formatted.inner_mac[3] << 24));
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addr_high = ((u32)input->formatted.inner_mac[4] |
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((u32)input->formatted.inner_mac[5] << 8));
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cloud_type |= addr_high;
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IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
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IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
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IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
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}
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/* configure FDIRHASH register */
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fdirhash = input->formatted.bkt_hash;
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@ -1935,6 +2000,11 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
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IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
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err = ixgbe_fdir_check_cmd_complete(hw);
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if (err) {
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DEBUGOUT("Flow Director command did not complete!\n");
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return err;
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}
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return IXGBE_SUCCESS;
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}
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@ -2378,6 +2378,9 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
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#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
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#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
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#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
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#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */
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#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */
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#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
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#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000
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#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
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@ -2393,6 +2396,13 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_FDIRM_L4P 0x00000008
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#define IXGBE_FDIRM_FLEX 0x00000010
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#define IXGBE_FDIRM_DIPv6 0x00000020
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#define IXGBE_FDIRM_L3P 0x00000040
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#define IXGBE_FDIRIP6M_INNER_MAC 0x03F0 /* bit 9:4 */
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#define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800 /* bit 11 */
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#define IXGBE_FDIRIP6M_TNI_VNI 0xF000 /* bit 15:12 */
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#define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000 /* bit 12 */
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#define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F /* bit 10, 3:0 */
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#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
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#define IXGBE_FDIRFREE_FREE_SHIFT 0
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