22827 Commits

Author SHA1 Message Date
Harman Kalra
0149ee8dc8 maintainers: update for interrupt subsystem
Updating MAINTAINERS file for interrupt subsystem.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-06-23 23:25:02 +02:00
Fady Bader
f6da77d92d meter: remove inline functions from export list
The code didn't compile when using exported meter functions under Windows.

error LNK2001: unresolved external symbol
rte_meter_srtcm_color_aware_check
error LNK2001: unresolved external symbol
rte_meter_srtcm_color_blind_check
error LNK2001: unresolved external symbol
rte_meter_trtcm_color_aware_check
error LNK2001: unresolved external symbol
rte_meter_trtcm_color_blind_check
error LNK2001: unresolved external symbol
rte_meter_trtcm_rfc4115_color_aware_check
error LNK2001: unresolved external symbol
rte_meter_trtcm_rfc4115_color_blind_check

The cause was that there were some inline functions that were included in
the export list.
To solve this the functions were removed from rte_meter_version.map export
list which are implemented in the header and shouldn't be exported.

Fixes: 655796d2b5fb ("meter: support RFC4115 trTCM")
Fixes: 9d41beed24b0 ("lib: provide initial versioning")
Cc: stable@dpdk.org

Signed-off-by: Fady Bader <fady@mellanox.com>
2020-06-23 19:29:41 +02:00
Fady Bader
540fbc2786 timer: support EAL functions on Windows
Implemented the needed Windows eal timer functions.

Signed-off-by: Fady Bader <fady@mellanox.com>
Reviewed-by: Tal Shnaiderman <talshn@mellanox.com>
Tested-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Ranjit Menon <ranjit.menon@intel.com>
2020-06-23 19:03:30 +02:00
Fady Bader
03437f2dc8 timer: move from common to Unix directory
EAL common timer doesn't compile under Windows.

Compilation log:
error LNK2019:
unresolved external symbol nanosleep referenced in function
rte_delay_us_sleep
error LNK2019:
unresolved external symbol get_tsc_freq referenced in function set_tsc_freq
error LNK2019:
unresolved external symbol sleep referenced in function set_tsc_freq

The reason was that some functions called POSIX functions.
The solution was to move POSIX dependent functions from common to Unix.

Signed-off-by: Fady Bader <fady@mellanox.com>
Reviewed-by: Tal Shnaiderman <talshn@mellanox.com>
Acked-by: Ranjit Menon <ranjit.menon@intel.com>
2020-06-23 18:33:20 +02:00
Dmitry Kozlyuk
26a6946a86 doc: clarify compilation with MinGW-w64
Provide a more direct link for installer download and clarify thread
model choice during installation. As pthread is not a requirement,
remove notice about its possible runtime dependency.

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Pallavi Kadam <pallavi.kadam@intel.com>
2020-06-23 16:41:06 +02:00
Dmitry Kozlyuk
a9bdee6ad9 config/x86: remove path for MinGW-w64 cross toolchain
Absolute paths in Meson cross-file impose unnecessary limitation
on build environment, remove them.

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Pallavi Kadam <pallavi.kadam@intel.com>
2020-06-23 16:40:24 +02:00
Dmitry Kozlyuk
9d8feca542 config: never link with pthread on Windows
Even if pthread is provided by the toolchain, it is not needed for DPDK
on Windows, because internal shim is used. As a side-effect, this
enables cross-build with MinGW configured with non-POSIX thread library,
e.g. mcfgthread, which is the default on some distributions.

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Pallavi Kadam <pallavi.kadam@intel.com>
2020-06-23 16:38:58 +02:00
Karra Satwik
2e40fdc2d3 net/cxgbe: always enable HASH filter support
Disable all unused firmware resources during init time to give
more resources for HASH (exact-match) filter region and always
request firmware to enable HASH filter support when resources
are available.

Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 20:12:35 +02:00
Ophir Munk
4f96d91396 net/mlx5/linux: add memory region callbacks to Verbs
Create a set of verbs callbacks in 'struct mlx5_verbs_ops'
and add MR operations to it (file net/mlx5/linux/mlx5_verbs.c).

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-06-17 16:32:01 +02:00
Ophir Munk
d5ed8aa944 net/mlx5: add memory region callbacks in per-device cache
Prior to this commit MR operations were verbs based and hard coded under
common/mlx5/linux directory. This commit enables upper layers (e.g.
net/mlx5) to determine which MR operations to use. For example the net
layer could set devx based MR operations in non-Linux environments. The
reg_mr and dereg_mr callbacks are added to the global per-device MR
cache 'struct mlx5_mr_share_cache'.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-06-17 16:32:01 +02:00
Ophir Munk
58a17853b5 common/mlx5: export memory region Verbs operations
The glue verbs operations reg_mr and dereg_mr are wrapped and exported
in functions mlx5_common_verbs_reg_mr and mlx5_common_verbs_dereg_mr
respectively.  The exported functions are added to a new file
linux/mlx5_common_verbs.c.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-06-17 16:32:01 +02:00
Ophir Munk
56d2067735 common/mlx5: remove memory region dependency on Verbs
Replace 'struct ibv_mr *' (in 'struct mlx5_mr') with a new 'struct
mlx5_pmd_mr'.  The new struct contains the required MR field: lkey,
addr, len and is independent of ibv.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-06-17 16:32:01 +02:00
Rahul Lakkireddy
ff7079a3a8 net/cxgbe: ignore flow default masks for unrequested fields
commit 536db938a444 ("net/cxgbe: add devargs to control filtermode and
filtermask") allows configuring hardware to select specific combination
of header fields to match in the incoming packets. However, the default
mask is set for all fields in the requested pattern items, even if the
field is not explicitly set in the combination and results in
validation errors. To prevent this, ignore setting the default masks
for the unrequested fields and the hardware will also ignore them in
validation, accordingly. Also, tweak the filter spec before finalizing
the masks.

Fixes: 536db938a444 ("net/cxgbe: add devargs to control filtermode and filtermask")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 15:31:32 +02:00
Rahul Lakkireddy
7fe1d0b459 net/cxgbe: fix SMT leak in filter error and free path
Free up Source MAC Table (SMT) entry properly during filter create
failure and filter delete.

Fixes: 993541b2fa4f ("net/cxgbe: support flow API for source MAC rewrite")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 15:31:32 +02:00
Rahul Lakkireddy
be5f4d5ced net/cxgbe: fix double MPS alloc by flow validate and create
The Multi Port Switch (MPS) entry is allocated twice when both
flow validate and create are invoked, but only freed once during
flow destroy. Avoid double alloc by moving MPS entry allocation
closer to when the filter create request is sent to hardware and
will be ignored for filter validate request.

Fixes: fefee7a619a4 ("net/cxgbe: add flow ops to match based on dest MAC")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 15:31:32 +02:00
Rahul Lakkireddy
e0e1496be5 net/cxgbe: fix L2T leak in filter error and free path
Free up Layer 2 Table (L2T) entry properly during filter create
failure and filter delete.

Fixes: 1decc62b1cbe ("net/cxgbe: add flow operations to offload VLAN actions")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 15:31:32 +02:00
Rahul Lakkireddy
844b21299f net/cxgbe: fix CLIP leak in filter error path
Free up Compressed Local IP (CLIP) entry properly during filter
creation failure path. Also consolidate all various tables
cleanup to a common function and invoke it from both wild-card
and exact-match filter paths.

Fixes: af44a577988b ("net/cxgbe: support to offload flows to HASH region")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
2020-06-17 15:31:32 +02:00
Qi Zhang
c5f5243d2e net/ice/base: remove PPPoD from PPPoE bitmap
Remove PPPoD's packet type from PPPoE's ptype bitmap.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
8c98e3c539 net/ice/base: update IPv4 and IPv6 flow packet type masks
In the flow API, add ability to add IPV4/IPV6 rules that match on
packets with or without inner L4 protocols.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
00d432ac4b net/ice/base: add 1G SGMII PHY type
There isn't a case for 1G SGMII in ice_get_media_type() so add
the handling for it.

Also handle the special case where some direct attach
cables may report that they support 1G SGMII, but
that is erroneous since SGMII is supposed to be a
backplane media type (between a MAC and a PHY). If
the driver doesn't handle this special case then a
user could see the 'Port' in ethtool change from
'Direct attach Copper' to 'Backplane' when they have
forced the speed to 1G, but the cable hasn't changed.

Lastly, change ice_aq_get_phy_caps() to save the
module_type info if the function was called with
ICE_AQC_REPORT_TOPO_CAP. This call uses the media
information to populate the module_type. If no
media is present then the values in module_type
will be 0.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
13f5e4562a net/ice/base: support E823L devices
Add support for E823L devices.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
383cb0d49c net/ice/base: fix initializing resource for field vector
This patch add initialization for prof_res_bm_init flag
to zero in order that the possible resource for field vector
in the package file can be initialized.(in ice_init_prof_result_bm)

Fixes: 453d087ccaff ("net/ice/base: add common functions")
Cc: stable@dpdk.org

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
0f8a51b6e3 net/ice/base: add more tunnel type for IPv4 and IPv6
This patch add more tunnel type definition ipv4/ipv6 packet,
it enable tcp/udp layer of ipv4/ipv6 as L4 payload but without
L4 dst/src port number as input set for switch filter rule.

For example:
we can download a switch rule to direct ipv4 packet with specific
source and destination ip address to queue index 1.
"eth / ipv4 src is 192.168.0.1 dst is 192.168.0.2 / udp /
end actions queue index 1 / end"
this type of rule will be matched with ipv4/udp file only.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
fda75f4c40 net/ice/base: fix reference count on VSI list update
The parameter ref_cnt is used for tracking how many
rules are reusing this VSI list, so it can only be
updated when a rule which using this list be deleted.

Fixes: f89aa3affa9e ("net/ice/base: support removing advanced rule")
Cc: stable@dpdk.org

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
fa98f411f3 net/ice/base: remove unused code for VSI list free
When free vsi list resource after vsi list update to empty, some
useless code in function ice_remove_vsi_list_rule() should be deleted.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
64767daf3c net/ice/base: add command to LLDP
Add support for LLDP forwarding to SW programming in FW
LLDP Filter Control is 0x0A0A.

Signed-off-by: Sharon Haroni <sharon.haroni@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
ea88e9fc22 net/ice/base: distribute Tx queues evenly
Distribute the tx queues evenly across all queue groups. This will
help the queues to get more equal sharing among the queues when all
are in use.

In the previous algorithm, the next queue group node will be picked up
only after the previous one filled with max children.
For example: if VSI is configured with 9 queues, the first 8 queues
will be assigned to queue group 1 and the 9th queue will be assigned to
queue group 2.

The 2 queue groups split the bandwidth between them equally (50:50).
The first queue group node will share the 50% bandwidth with all of
its children (8 queues). And the second queue group node will share
the entire 50% bandwidth with its only children.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
69e618a753 net/ice/base: adjust scheduler default bandwidth weight
By default the queues are configured in legacy mode. The default
bandwidth settings for legacy/advanced modes are different. The existing
code was using the advanced mode default value of 1 which was
incorrect. This caused the unbalanced BW sharing among siblings.
The recommended default value is applied.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
f878b14865 net/ice/base: clear error status before set FC
ice_set_fc takes a u8 pointer 'aq_failures' as an input parameter. If
this function encounters an error, in addition to returning an
appropriate ice_status enum code, it also populates aq_failures with a
link specific error value.

If the caller does not initialize this variable to 0 before calling
ice_set_fc, it would appear as if ice_set_fc returned an error code in
this variable. So initialize it to 0.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
79d4730481 net/ice/base: avoid PPPoE IPv4 overlap
When PPPoE header is not selected, PPPoE should not be included in
ipv4 ptype bitmaps.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
b952bf867f net/ice/base: support checking all autoneg enable bits
struct ice_aqc_get_phy_caps_data has multiple autoneg enable bits.
ice_is_phy_caps_an_enabled checks all bits and returns true if any
autoneg enable bits are set.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
1565a51e50 net/ice/base: remove unimplemented function prototypes
There are no implementations for these two functions so remove the
prototypes.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
8cff19be5e net/ice/base: add entries in profile TCAM with priority
The profile TCAM tables are implemented such that entries with a smaller
index in the table have a higher priority. When records to be added to
the table have flags to differentiate between standard PTG and VSIG
records, then these entries need to have higher priority in order to be
found and processed first.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
be45049b3c net/ice/base: fix memory leak on error path
Handles memory leaks during control queue initialization and
buffer allocation failures. The MACRO - ICE_FREE_CQ_BUFS is modified to
re-use for this fix.

Fixes: 6c1f26be50a2 ("net/ice/base: add control queue information")
Cc: stable@dpdk.org

Signed-off-by: Surabhi Boob <surabhi.boob@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
064109fd2d net/ice/base: remove unneeded variable
The variable 'adj' is initialized to 0 and later used in an addition,
but the value is never changed from 0. Remove the variable since it's
doing nothing.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
4f13a6735f net/ice/base: fix return value
Function ice_rem_adv_rule_id return incorrect error code (ICE_ERR_PARAM)
whereas it should have returned ICE_ERR_DOES_NOT_EXIST return code
if filter list is empty or unable to find "rule" in list

Fixes: f89aa3affa9e ("net/ice/base: support removing advanced rule")
Cc: stable@dpdk.org

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
1b651a2a1d net/ice/base: update VSI handle to remaining VSI
When removing VSI from VSI list, if only one VSI left, we need
to downgrade a switch rule's action from "to VSI LIST" to "to VSI",
So, needs to update the VSI handle to the last remaining VSI for the
new action but not the first VSI be added to the list.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
803373cc94 net/ice/base: add rate limiter profile bit mask check
Mask bits before accessing the rate limiting profile type field.

Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
12b8bb04b4 net/ice/base: reset capabilities before parsing
The capability flags used to report whether an NVM component has
a pending update are stored as simple booleans. If ice_parse_caps finds
the relevant capability then the boolean is set to true.

If the capability is not provided by firmware, then the boolean value
will be left alone. This works during initialization because the
capabilities structure is zero-initialized.

However, this does not work if capabilities are updated by calling
ice_get_caps again after driver load. For example, consider if firmware
had a pending update, and then an EMPR was triggered. The update will
complete, and firmware will no longer report these capabilities.

However, the device driver will have already set the pending flags.
After an EMPR, new capabilities are read. However, because the pending
flags in the dev_caps.common_cap structure have already been set, they
will remain true.

Fix this by clearing the capabilities structures in ice_parse_caps
before processing any capabilities.

This ensures that the capabilities structure will always be refreshed to
match the state of the device or function capabilities reported by
firmware.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
94c81be833 net/ice/base: fix advanced switch rule stale information
To avoid having stale information about "adv_rule" per recipe, when all
rules associated to a given recipe are deleted, reset the "adv_rule"
flag otherwise it causes problem later on when decisions about filter
rules being present or not are made based on "adv_rule" flag.

Removed setting "adv_rule = 1" when recipe is created. It is set
correctly when advanced switch rule is added referring to the recipe
which was created as a result of adding advanced switch rule.

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
8a2989969a net/ice/base: support more PPPoE packet type
This patch add more dummy packet type for PPPoE packet,
it enable tcp/udp layer of IPv4/IPv6 for PPPoE payload,
so we can use L4 dst/src port as input set for switch
filter.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
0176d92a83 net/ice/base: remove unnecessary case branches
Remove unnecessary case branch, since the switch and pipeline stage is
not designed to be handled by the flow module.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
6bad5047be net/ice/base: return correct error code
Return ICE_ERR_DOES_NOT_EXIST return code if admin command error code is
ICE_AQ_RC_ENOENT (not exist). ice_aq_sw_rules is used when switch
rule is getting added/deleted/updated. In case of delete/update
switch rule, admin command can return ICE_AQ_RC_ENOENT error code
if such rule does not exist, hence return ICE_ERR_DOES_NOT_EXIST error
code from ice_aq_sw_rule, so that caller of this function can decide
how to handle ICE_ERR_DOES_NOT_EXIST.

Allow proper cleanup of internal data structures from ice_rem_adv_rule
function if ice_aq_sw_rules return error code ICE_ERR_DOES_NOT_EXIST
otherwise per recipe:rule list will never become empty.

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
6dfe33fbe5 net/ice/base: add debug logs
Add debug logs for ice_aq_get_phy_caps(), and format
ice_aq_set_phy_cfg() and ice_aq_get_link_info() debug logs to make them
more readable.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
38f165b161 net/ice/base: use macro for sizeof
The definition of ICE_SW_RULE_RX_TX_ETH_HDR_SIZE open codes the size of
a structure field. Replace this with the use of FIELD_SIZEOF.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
09ada7c890 net/ice/base: support RSS IPv6 prefix
Some IPv6 prefix related fields are defined in this patch, so that we
can use prefixes instead of full IPv6 address for RSS. These prefixes
include the first 32, 48, 64 bits of both SRC and DST IPV6 address.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
b2d192fccd net/ice/base: adjust function signature style format
Where possible, cuddle multiple lines of function signatures to be
consistent throughout the code.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
06d1a56251 net/ice/base: remove unnecessary braces
This patch mainly does cleanups related to unnecessary braces.
There might be different opinion to keep braces if more than
single line, but the purpose here is trying to sync DPDK's base
code with kernel's copy and its more convenient for future update.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
9c99297895 net/ice/base: give time for package download after PF reset
To allow for resets during package download, increase the timeout period
after performing a PF Reset. The time waited is the global config lock
timeout plus the normal PFSWR timeout.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00
Qi Zhang
10fb4bb74b net/ice/base: allow GENEVE and VXLAN rules with VLAN
When programming GENEVE and VXLAN switch rules, there are some instances
where both VLAN tagged packets plus non-VLAN tagged packets are needed
to match the rule.

In order to perform this action in one rule, the switch code needs
to setup the packet flag mask to ignore the VLAN packet flag. This
will allow the rule to match both VLAN and non-VLAN packets.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-06-16 19:21:08 +02:00