It fixes the issue of not configuring rss key enable flags
when there is no rss key available.
Fixes: 647d1eaf758b ("i40evf: support AQ based RSS config")
Signed-off-by: Helin Zhang <helin.zhang@intel.com>
If use DPDK PF + DPDK VF on igb NICs, we find the MAC address of VF
port is always 0. Because we forget to give it a value if this MAC
address is not assigned by PF. This patch'll assign a random MAC
address to igb VF port as ixgbe does.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This patch provides the initial implementation of the AES-NI multi-buffer
based crypto poll mode driver using DPDK's new cryptodev framework.
This PMD is dependent on Intel's multibuffer library, see the whitepaper
"Fast Multi-buffer IPsec Implementations on Intel® Architecture
Processors", see ref 1 for details on the library's design and ref 2 to
download the library itself. This initial implementation is limited to
supporting the chained operations of "hash then cipher" or "cipher then
hash" for the following cipher and hash algorithms:
Cipher algorithms:
- RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported)
Authentication algorithms:
- RTE_CRYPTO_AUTH_SHA1_HMAC
- RTE_CRYPTO_AUTH_SHA256_HMAC
- RTE_CRYPTO_AUTH_SHA512_HMAC
- RTE_CRYPTO_AUTH_AES_XCBC_MAC
Important Note:
Due to the fact that the multi-buffer library is designed for
accelerating IPsec crypto operation, the digest's generated for the HMAC
functions are truncated to lengths specified by IPsec RFC's, ie RFC2404
for using HMAC-SHA-1 with IPsec specifies that the digest is truncate
from 20 to 12 bytes.
Build instructions:
To build DPDK with the AESNI_MB_PMD the user is required to download
(ref 2) and compile the multi-buffer library on there system before
building DPDK. The environmental variable AESNI_MULTI_BUFFER_LIB_PATH
must be exported with the path where you extracted and built the multi
buffer library and finally set CONFIG_RTE_LIBRTE_PMD_AESNI_MB=y in
config/common_linuxapp.
Current status: It's doesn't support crypto operation
across chained mbufs, or cipher only or hash only operations.
ref 1:
https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-technology/fast-multi-buffer-ipsec-implementations-ia-processors-p
ref 2: https://downloadcenter.intel.com/download/22972
Signed-off-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
This patch adds a PMD for the Intel Quick Assist Technology DH895xxC
hardware accelerator.
This patch depends on a QAT PF driver for device initialization. See
the file docs/guides/cryptodevs/qat.rst for configuration details
This patch supports a limited subset of QAT device functionality,
currently supporting chaining of cipher and hash operations for the
following algorithmsd:
Cipher algorithms:
- RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported)
Hash algorithms:
- RTE_CRYPTO_AUTH_SHA1_HMAC
- RTE_CRYPTO_AUTH_SHA256_HMAC
- RTE_CRYPTO_AUTH_SHA512_HMAC
- RTE_CRYPTO_AUTH_AES_XCBC_MAC
Some limitation on this patchset which shall be contributed in a
subsequent release:
- Chained mbufs are not supported.
- Hash only is not supported.
- Cipher only is not supported.
- Only in-place is currently supported (destination address is
the same as source address).
- Only supports session-oriented API implementation (session-less
APIs are not supported).
Signed-off-by: Declan Doherty <declan.doherty@intel.com>
Signed-off-by: John Griffin <john.griffin@intel.com>
Signed-off-by: Des O Dea <des.j.o.dea@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Without .map file, compiling error occurs when
CONFIG_RTE_BUILD_SHARED_LIB is enabled.
Reported-by: Guo Xin <gxin@ezchip.com>
Signed-off-by: Zhigang Lu <zlu@ezchip.com>
Secondary processes are expected to use queues and other resources
allocated by the primary, however Verbs resources can only be shared
between processes when inherited through fork().
This limitation can be worked around for TX by configuring separate queues
from secondary processes.
Signed-off-by: Or Ami <ora@mellanox.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
The number of available entries in TX rings is taken before performing
completion, effectively making rings smaller than they are and causing
TX performance issues under load.
Fixes: 2e22920b85d9 ("mlx5: support non-scattered Tx and Rx")
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
The number of available entries in TX rings is taken before performing
completion, effectively making rings smaller than they are and causing
TX performance issues under load.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
When MP to MR cache is full, the last (newest) MR is freed instead of the
first (oldest) one, causing local protection errors during TX.
Fixes: 2e22920b85d9 ("mlx5: support non-scattered Tx and Rx")
Signed-off-by: Olga Shern <olgas@mellanox.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
When MP to MR cache is full, the last (newest) MR is freed instead of the
first (oldest) one, causing local protection errors during TX.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Signed-off-by: Olga Shern <olgas@mellanox.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Pre-registering mbuf memory pools when creating TX queues avoids costly
registrations later in the data path.
Fixes: 2e22920b85d9 ("mlx5: support non-scattered Tx and Rx")
Signed-off-by: Olga Shern <olgas@mellanox.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Pre-registering mbuf memory pools when creating TX queues avoids costly
registrations later in the data path.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Signed-off-by: Olga Shern <olgas@mellanox.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Buffers with too many segments are linearized to overcome
MLX5_PMD_SGE_WR_N, unfortunately the last segment is never sent.
Fixes: 3ee8444608a9 ("mlx5: support scattered Rx and Tx")
Signed-off-by: Jesper Wramberg <jesper.wramberg@gmail.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Buffers with too many segments are linearized to overcome
MLX4_PMD_SGE_WR_N, unfortunately the last segment is never sent.
Fixes: be11b35817e0 ("mlx4: move scattered Tx processing to helper function")
Signed-off-by: Jesper Wramberg <jesper.wramberg@gmail.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Indirect mbuf data may come from a different mempool which must be
registered separately as another memory region, otherwise such mbufs cannot
be sent.
Fixes: 2e22920b85d9 ("mlx5: support non-scattered Tx and Rx")
Signed-off-by: Jesper Wramberg <jesper.wramberg@gmail.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Indirect mbuf data may come from a different mempool which must be
registered separately as another memory region, otherwise such mbufs cannot
be sent.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Signed-off-by: Jesper Wramberg <jesper.wramberg@gmail.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
A typo causes TX stats indices to be retrieved from RX queues.
Fixes: 87011737b715 ("mlx5: add software counters")
Reported-by: Nicolas Harnois <nicolas.harnois@6wind.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
A typo causes TX stats indices to be retrieved from RX queues.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Reported-by: Nicolas Harnois <nicolas.harnois@6wind.com>
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
CXGBE PMD depends on an alarm to periodically transmit any pending
coalesced packets and hence spins for a lock for each tx queue in the
alarm callback.
A better solution is to try to get a lock whenever possible, instead
of spinning for it.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Most dpdk examples and apps seem to initialize with a minimum of 128 rx
descriptors and 512 tx descriptors for queue setup. However, CXGBE PMD
enforces a minimum of 1024 descriptors. This causes the dpdk stack
to return -EINVAL because the apps do not request the minimum required.
The fix is to relax this enforcing in CXGBE PMD. A minimum of 128
descriptors seems to be a good number with the least impact on the
performance.
Fixes: 946c9ed95616 ("cxgbe: get descriptor limits")
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
The vector number may change during 'dev_start'. Before enabling a new vector mapping,
it's necessary to disable/unmap the previous setting.
Fixes: 7ab8500037f6 ("ixgbe: fix VF start with PF stopped")
Reported-by: Yong Liu <yong.liu@intel.com>
Signed-off-by: Cunming Liang <cunming.liang@intel.com>
Tested-by: Yong Liu <yong.liu@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
The vector number may change during 'dev_start'.
Before enabling a new vector mapping,
it's necessary to disable/unmap the previous setting.
Fixes: fe685de2b1b6 ("igb: fix VF start with PF stopped")
Reported-by: Yong Liu <yong.liu@intel.com>
Signed-off-by: Cunming Liang <cunming.liang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
fm10k driver will meet compile error on non-x86 platforms due to
SSE instructions. Original implementation didn't have switch to
turn off vPMD.
The improvement introduces a macro to turn on/off vPMD functions,
it's on by default. On non-x86 platforms, it can simply be turned
off to fix compile issue.
Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
When the fm10k port is closed, both func tx_queue_clean() and
fm10k_tx_queue_release_mbufs_vec() will try to release buffer in
SW ring. The latter func won't do sanity check on those pointers
and cause crash.
The fix removed Vector TX buffer release func since it can share
the release functions with regular TX.
Fixes: fb9066e479a6 ("fm10k: reset and release mbuf for vector Tx")
Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
Acked-by: Michael Qiu <michael.qiu@intel.com>
vlan_tci should be copied from RX descriptor to mbuf,
and flag PKT_RX_VLAN_PKT should be set for every RX packet,
this patch fixes this issue.
Packets in fm10k device always carry at least one VLAN tag.
For those packets coming in without VLAN tag,
the port default VLAN tag will be used.
So in fm10k, always PKT_RX_VLAN_PKT flag is set and vlan_tci
is valid for each RX packet's mbuf.
Signed-off-by: Shaopeng He <shaopeng.he@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush
configuration but not I40E_WRITE_FLUSH. This patch fixed this issue.
Fixes: be6c228d4da3 (i40evf: support Rx interrupt)
Reported-by: Qian Xu <qian.q.xu@intel.com>
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
If DCB is not enabled, the BW info is not stored for VSI. This
patch fixes this issue by merging functions i40e_vsi_dump_bw_config
and i40e_vsi_get_bw_info together.
Fixes: c8b9a3e3fe1b (i40e: support DCB mode)
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
When NVM version is updated to 5.x, DCB can not be configured. This
issue is because of the FW version validation is not correct.
This patch fixed this issue.
Fixes: c8b9a3e3fe1b (i40e: support DCB mode)
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Tested-by: Yulong Pei <yulong.pei@intel.com>
As firmware does not support any link control from software driver
side, any phy config should be ignored as a workaround. Otherwise
the link might not be up again after binding back to kernel driver.
Signed-off-by: Helin Zhang <helin.zhang@intel.com>
It fixes the issue of not re-configuring hash enable flags (HENA)
if there is no key.
Fixes: d0a349409bd7 ("i40e: support AQ based RSS config")
Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This patch removes the crc bytes from byte counter statistics.
Doing so fixes a bug that CRC bytes were included on TX but not
on RX, causing mismatch of bytes received / sent.
Fixes: 9aace75fc82e ("i40e: fix statistics")
Reported-by: Weichun Chen <weichunx.chen@intel.com>
Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This patch removes the crc bytes from byte counter statistics.
Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This patch removes the crc bytes from byte counter statistics.
Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This fixes a bug added to em and igb drivers which causes the pci info
seen by the primary process to become invalidated by secondary process
startup.
This call was added after the process type check in the other drivers.
Fixes: eeefe73f0af1 ("drivers: copy PCI device info to ethdev data")
Signed-off-by: Jon DeVree <nuxi@vault24.org>
Acked-by: Bernard Iremonger <bernard.iremonger@intel.com>
When freeing the device it is also neccesary to free
rx_queues and tx_queues
Signed-off-by: Mauricio Vasquez B <mauricio.vasquezbernal@studenti.polito.it>
Add virtual PMD which communicates with COMBO cards through sze2
layer using libsze2 library.
Since link_speed is uint16_t, there can not be used number for 100G
speed, therefore link_speed is set to ETH_LINK_SPEED_10G until the
type of link_speed is solved.
Signed-off-by: Matej Vido <matejvido@gmail.com>
This commit introduce rte_smp_mb(), rte_smp_wmb() and rte_smp_rmb(), in
order to enable memory barriers between lcores.
The patch does not provide any functional change for IA, the goal is to
have infrastructure for weakly ordered machines like ARM to work on DPDK.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Add additional functions to support the existing IEEE1588
functionality and to enable getting, setting and adjusting
the device time.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Reviewed-by: John McNamara <john.mcnamara@intel.com>
Add additional functions to support the existing IEEE1588
functionality and to enable getting, setting and adjusting
the device time.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Reviewed-by: John McNamara <john.mcnamara@intel.com>
Add additional functions to support the existing IEEE1588
functionality and to enable getting, setting and adjusting
the device time.
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Reviewed-by: John McNamara <john.mcnamara@intel.com>
Use common code to handle Xen support at runtime.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Jijiang Liu <jijiang.liu@intel.com>
These statistics are marked deprecated, leave them alone.
Also keep track of imissed across all ports.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
