Adding initial support for programming NPC. NPC is Network Parser
and CAM unit that provides Rx and Tx packet parsing and packet
manipulation functionality on Marvell CN9K and CN10K SoC's. It is
mapped to RTE Flow in DPDK.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Add support to dump TM HW registers and hierarchy on error.
This patch also adds support for misc utils such as API to
query TM HW resource availability, resource pre-allocation
and static priority support on root node.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support for dynamic node update of shaper profile,
RR quantum and also support to suspend or resume an active
TM node.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to create internal TM default hierarchy and ratelimit
hierarchy and API to ratelimit SQ to a given rate. This will be
used by cnxk ethdev driver's tx queue ratelimit op.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to enable or disable hierarchy along with
allocating node HW resources such as shapers and schedulers
and configuring them to match the user created or default
hierarchy.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to add/delete/update shaper profile for
a given NIX. Also add support to walk through existing
shaper profiles.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Add support to add/delete nodes in a hierarchy.
This patch also adds misc utils to get node name,
walk through nodes etc.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Add nix traffic management base support to init/fini node, shaper profile
and topology, setup SQ for a given user hierarchy or default internal
hierarchy.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to create LSO formats for TCP segmentation offload
for IPv4/IPv6, tunnel and non-tunnel protocols. Tunnel protocol
support is for GRE and UDP based tunnel protocols.
This patch also adds other helper API to retrieve eeprom info
and configure Rx for different switch headers.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to enable/disable Rx/Tx flow control and pause
frame configuration on NIX.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add helper API to support VLAN filtering and stripping
on Rx and VLAN insertion on Tx.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to dump NIX RQ, SQ and CQ contexts apart
from NIX LF registers.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support for retrieving NIX extended stats that are
per NIX LF and per LMAC.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add API to provide Rx and Tx stats for a given NIX.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to enable/disable Rx and Tx PTP timestamping
support. Also provide API's to register ptp info callbacks
to get config change update from Kernel.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add API's for default/non-default reta table setup,
key set/get, and flow algo setup for CN9K and CN10K.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add NIX specific NPC operations such as NPC mac address get/set,
mcast entry add/delete, promiscuous mode enable/disable etc.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to different MAC related operations such as
MAC address set/get, link set/get, link status callback,
etc.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This patch adds support to init/modify/fini NIX
SQ(send queue) for both CN9K and CN10K platforms.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add nix Rx queue management API to init/modify/fini
RQ context and also setup CQ(completion queue) context.
Current support is both for CN9K and CN10K devices.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to register NIX error and completion
queue IRQ's using base device class IRQ helper API's.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Add base nix support as ROC(Rest of Chip) API which will
be used by generic ETHDEV PMD(net/cnxk).
This patch adds support to device init, fini, resource
alloc and free API which sets up a ETHDEV PCI device of either
CN9K or CN10K Marvell SoC.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Add APIs to do allocations/frees in batch from
NPA pool.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add APIs to alloc/free in bulk from NPA pool.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add base NPA device support. NPA i.e Network Pool Allocator is
HW block that provides HW mempool functionality on Marvell CN9K
and CN10K SoC's. NPA by providing HW mempool support, also
facilitates Rx and Tx packet alloc and packet free by HW without
SW intervention.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add VF specific handling such as BAR4 setup, forwarding
VF mbox messages to AF and vice-versa, VF FLR handling
etc.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Introduce 'dev' class to hold cnxk PCIe device specific
information and operations.
All PCIe drivers(ethdev, mempool, cryptodev and eventdev) of cnxk
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, LMT setup, VF message
mbox forwarding, etc.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This patch adds mailbox infra API's to communicate with Kernel AF
driver. These API's will be used by all the other cnxk drivers
for mbox init/fini, send/recv functionality.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.
This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Add interrupt helper API's in common code to register and
unregister for specific interrupt vectors. These API's
will be used by all cnxk drivers.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support for registering callbacks for roc plt init.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add routines for SoC model identification and HW IO handling
routines specific to CN9K and CN10K Marvell SoC's.
These are based on arm64 ISA and behaviour specific to
Marvell SoC's.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add meson build infrastructure along with HW definition
header file.
This patch also adds cross-compile configs for arm
for CN9K series and CN10K series of Marvell SoC's.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
The checking of symbols within each library and driver is only of
interest to developers, so limit to developer mode only.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The messages about what components have what dependency names, and
information about function versioning not being supported on windows are
only of interest to developers, so hide them when building in
non-developer mode.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The log messages had various issues:
- split on 2 lines, making search (grep) difficult
- long lines (can be split after the string)
- indented for no good reason (parent message may have higher log level)
- inconsistent use of __func__, not meaningful context for user
- lack of context (general message not mentioning VFIO)
- log level too high (more below)
Message having its level decreased from WARNING to NOTICE:
"not managed by VFIO driver, skipping"
Message having its level decreased from INFO to DEBUG:
"Probing VFIO support..."
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
UMR (User-Mode Memory Registration) WQE can present data buffers
scattered within multiple mbufs with single indirect mkey. Take
advantage of the UMR WQE, scattered mbuf in one operation can be
presented to an indirect mkey. The RegEx which only accepts one
mkey can now process the whole scattered mbuf in one operation.
The maximum scattered mbuf can be supported in one UMR WQE is now
defined as 64. The mbufs from multiple operations can be combined
into one UMR WQE as well if there is enough space in the KLM array,
since the operations can address their own mbuf's content by the
mkey's address and length. However, one operation's scattered mbuf's
can't be placed in two different UMR WQE's KLM array, if the UMR
WQE's KLM does not has enough free space for one operation, the
extra UMR WQE will be engaged.
In case the UMR WQE's indirect mkey will be over wrapped by the SQ's
WQE move, the mkey's index used by the UMR WQE should be the index
of last the RegEX WQE in the operations. As one operation consumes
one WQE set, build the RegEx WQE by reverse helps address the mkey
more efficiently. Once the operations in one burst consumes multiple
mkeys, when the mkey KLM array is full, the reverse WQE set index
will always be the last of the new mkey's for the new UMR WQE.
In GGA mode, the SQ WQE's memory layout becomes UMR/NOP and RegEx
WQE by interleave. The UMR and RegEx WQE can be called as WQE set.
The SQ's pi and ci will also be increased as WQE set not as WQE.
For operations don't have scattered mbuf, uses the mbuf's mkey directly,
the WQE set combination is NOP + RegEx.
For operations have scattered mbuf but share the UMR WQE with others,
the WQE set combination is NOP + RegEx.
For operations complete the UMR WQE, the WQE set combination is UMR +
RegEx.
Signed-off-by: John Hurley <jhurley@nvidia.com>
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The log levels are configured by using the name of the logs.
Some drivers are aligned to follow a common log name standard:
pmd.class.driver[.sub]
Some "common" drivers skip the "class" part:
pmd.driver.sub
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
Acked-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Min Hu (Connor) <humin29@huawei.com>
When compiled as a shared object, and loaded at runtime as a plugin,
the drivers should get the log level set earlier at EAL init
by the user through --log-level option.
The function for applying the log level setting is
rte_log_register_type_and_pick_level().
It is called by most drivers via RTE_LOG_REGISTER().
The drivers common/mlx5, bcmfs and e1000 were missing,
so the user-specified log level was not applied when
those drivers were loaded as plugins.
The macro RTE_LOG_REGISTER() is used for those drivers.
The unnecessary protection for double registration
is removed from e1000.
Fixes: 9c99878aa1b1 ("log: introduce logtype register macro")
Fixes: c8e79da7c676 ("crypto/bcmfs: introduce BCMFS driver")
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Rather than have two files that keeps getting out of sync, let's
annotate the version.map to generate the Windows export file.
Some mlx5 symbols (haswell_broadwell_cpu, mlx5_glue, mlx5_os_*) were
only exported for Windows.
All of them are available and used by Linux too, so this patch adds
them in version.map.
Note: Existing version.map annotation achieved with:
$ for dir in lib/librte_eal drivers/common/mlx5; do
./buildtools/map-list-symbol.sh $dir/*.map |
while read file version sym; do
! git grep -qw $sym $dir/*.def || continue;
sed -i -e "s/$sym;/$sym; # WINDOWS_NO_EXPORT/" $dir/*.map;
done;
done
Signed-off-by: David Marchand <david.marchand@redhat.com>
Tested-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Avoid race with unregister interrupt handler if interrupt
source has some active callbacks at the moment, use wrapper
around rte_intr_callback_unregister() to check for -EAGAIN
return value and to loop until rte_intr_callback_unregister()
succeeds.
Signed-off-by: Renata Saiakhova <renata.saiakhova@ekinops.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Harman Kalra <hkalra@marvell.com>
The names of the prototypes pci_probe_t and pci_remove_t
are missing a prefix rte_.
These function types are simply renamed.
No compatibility break is expected for the applications
because it is considered as an internal name in the driver interface.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
The name of the constant PCI_ANY_ID was missing RTE_ prefix.
It is renamed, and the old name becomes a deprecated alias.
While renaming, the duplicate definitions in rte_bus_pci.h
are removed to keep only those in rte_pci.h.
Note: rte_pci.h is included in rte_bus_pci.h
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
