Insert get_physaddr() into public API as rte_mem_virt2phy().
rte_mem_virt2phy() permits to obtain the physical address of any
virtual address mapped to the current process.
get_physaddr() was working only for addresses pointing exactly to
the first byte of a page.
Note that this function is very slow and shouldn't be called
after initialization to avoid a performance bottleneck.
The memory must be locked with mlock(). The function rte_mem_lock_page()
is a mlock() helper that lock the whole page.
A better name would be rte_mem_virt2phys but rte_mem_virt2phy is more
consistent with rte_mempool_virt2phy.
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
This reverts commit 57c24af85d9eaa81549a212169605b4e2468a29f
which was wrongly rebased in 1.6.0 branch:
- commit log must be changed for 1.6.0
- it breaks building for 32-bit
A new version of this commit has to be done.
Applications can test versions, for compatibility, this way:
#if RTE_VERSION >= RTE_VERSION_NUM(1,2,3,4)
RTE_VERSION was already defined for use with rte_config.
It is moved in rte_version.h and updated to current version number.
Note that the first tag having this helper is 1.2.3r2.
Releases r0 have not this patch.
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
Intel 82546EB Gigabit ethernet controller is reported to be working
with copper.
Tested-by: Ognjen Joldzic <ognjen.joldzic@gmail.com>
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Some devices need to be unbound in order to be used via the PMD
without kernel module.
Signed-off-by: Damien Millescamps <damien.millescamps@6wind.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Since DPDK 1.4, if RTE_EAL_UNBIND_PORTS is disabled, igb_uio mapping is
done for all devices (commit eee16c964cd), breaking some non-Intel drivers.
But pci_uio_map_resource() should only be called for Intel devices
(using igb_uio kernel module).
The flag RTE_PCI_DRV_NEED_IGB_UIO is set for all those devices, even when
RTE_EAL_UNBIND_PORTS is disabled (fixes commit a22f5ce8fcc).
Signed-off-by: David Marchand <david.marchand@6wind.com>
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Damien Millescamps <damien.millescamps@6wind.com>
Allow external libraries and applications to know if hugepages
are enabled.
Signed-off-by: Damien Millescamps <damien.millescamps@6wind.com>
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
When huge pages are disabled, memory is allocated for a single, undefined
CPU socket using malloc(), causing rte_memzone_reserve_aligned() to fail
most of the time.
This patch causes that memory to use SOCKET_ID_ANY instead of 0, and allow
it to be used in place of any socket ID specified by user.
Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Damien Millescamps <damien.millescamps@6wind.com>
Remove an error log in memzone_reserve_aligned_thread_unsafe().
It is up to the caller to log the error, and this is already done
in DPDK code (especially in network drivers).
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Extract rte_mem_virt2phy() from get_physaddr().
rte_mem_virt2phy() permits to obtain the physical address of any
virtual address mapped to the current process calling this function.
Note that this function is very slow and shouldn't be called
after initialization to avoid a performance bottleneck.
The memory must be locked with mlock(). The function rte_mem_lock_page()
is a mlock() helper that lock the whole page.
A better name would be rte_mem_virt2phys but rte_mem_virt2phy is more
consistent with rte_mempool_virt2phy.
Signed-off-by: Damien Millescamps <damien.millescamps@6wind.com>
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
According to Intel Developer's Manual:
"The RDTSC instruction is not a serializing instruction. It does not necessarily wait
until all previous instructions have been executed before reading the counter. Simi-
larly, subsequent instructions may begin execution before the read operation is
performed. If software requires RDTSC to be executed only after all previous instruc-
tions have completed locally, it can either use RDTSCP (if the processor supports that
instruction) or execute the sequence LFENCE;RDTSC."
So add a rte_rdtsc_precise function that do a memory barrier before rdtsc to
synchronize operations and ensure that the TSC read is done at the expected place.
Use r/w memory barrier instead of lfence to serialize both loads and stores.
Signed-off-by: Didier Pallard <didier.pallard@6wind.com>
Reviewed-by: François-Frédéric Ozog <ff@ozog.com>
Reviewed-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Adding or subtracting a value to a pointer makes a new pointer
of unknown type.
So typeof() is replaced by (void*) in RTE_PTR_ADD() and RTE_PTR_SUB().
But RTE_PTR_ALIGN_* macros have in their explicit API to return a pointer
of the same type. Since RTE_PTR_ALIGN_CEIL is based on RTE_PTR_ADD, a
typeof() is added to keep the original behaviour.
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
- rte_panic must be before rte_panic_ to be associated to its doc
- marker /**< must be used when commenting after the declaration only
- fix rte_string_fns.h title
- typos
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
This provides a para-virtualization packet switching solution, based on the
Xen hypervisor’s Grant Table, which provides simple and fast packet
switching capability between guest domains and host domain based on
MAC address or VLAN tag.
This solution is comprised of two components; a Poll Mode Driver (PMD)
as the front end in the guest domain and a switching back end in the
host domain. XenStore is used to exchange configure information
between the PMD front end and switching back end,
including grant reference IDs for shared Virtio RX/TX rings, MAC
address, device state, and so on.
The front end PMD can be found in the Intel DPDK directory lib/
librte_pmd_xenvirt and back end example in examples/vhost_xen.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Core support for using the Intel DPDK with Xen Dom0 - including EAL
changes and mempool changes. These changes encompass how memory mapping
is done, including support for initializing a memory pool inside an
already-allocated block of memory.
KNI sample app updated to use KNI close function when used with Xen.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
These library changes provide a new Intel DPDK feature for communicating
with virtual machines using QEMU's IVSHMEM mechanism.
The feature works by providing a command line for QEMU to map several hugepages
into a single IVSHMEM device. For the guest to know what is inside any given IVSHMEM
device (and to distinguish between Intel(R) DPDK and non-Intel(R) DPDK IVSHMEM
devices), a metadata file is also mapped into the IVSHMEM segment. No work needs to
be done by the guest application to map IVSHMEM devices into memory; they are
automatically recognized by the Intel(R) DPDK Environment Abstraction Layer (EAL).
Changes in this patch:
* Changes to EAL to allow mapping of all hugepages in a memseg into a single file
* Changes to EAL to allow ivshmem devices to be transparently mapped in
the process running on the guest.
* New ivshmem library to create and manage metadata exported to guest VM's
* New ivshmem compilation targets
* Mempool and ring changes to allow export of structures to a VM and allow
a VM to attach to those structures.
* New autotests to unit tests this functionality.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
For certain functionality, e.g. Xen Dom0 support, it is required that
we can guarantee that memzones for descriptor rings won't cross 2M
boundaries. So add new memzone reserve function where we can pass in a
boundary condition parameter.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Extra space for future alignment was reserved twice.
It was introduced in version 1.3.0 (commit 916e4f4f4e45a1d3cdd473cf9ef).
Signed-off-by: Pei Chao <peichao85@gmail.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Added the following new macros/inline functions, which are both
generally useful and needed for later functionality:
* rte_align64pow2: aligns a 64bit parameter to next power of 2
* RTE_LEN2MASK: create mask of type <tp> with the first <ln> bits
* RTE_DIM: return the number of elements in an array.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The rte_ring functions used a compiler barrier to stop the compiler
reordering certain expressions. This is generally useful so is moved
to the common header file with the other barriers.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Changes to allow compilation and use on FreeBSD. Includes:
* contigmem and nic_uio driver for FreeBSD
* new EAL instance
* new "bsdapp" compilation target
* various compilation fixes due to differences between linux and freebsd
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The base driver supports more NICs:
- i210 flashless
- i217
- i218
- i354
The new features are not automatically used by the DPDK PMD.
Signed-off-by: Intel
This type of pseudo-device is needed for ring and pcap PMDs.
They are compatible with whitelist and are initialized in rte_eal_init().
Signed-off-by: Intel
The pause instruction is part of SSE2 extensions.
Note that some compilers define _mm_pause as "rep; nop" instead of "pause".
For compatible processors, they are equivalent.
http://www.intel.com/Assets/PDF/manual/325383.pdf:
"
When executing a spin-wait loop, a Pentium 4 or Intel Xeon processor suffers
a severe performance penalty when exiting the loop because it detects a
possible memory order violation.
The PAUSE instruction provides a hint to the processor that the code sequence
is a spin-wait loop. The processor uses this hint to avoid the memory order
violation in most situations, which greatly improves processor performance.
"
Signed-off-by: Intel
