For larger packet size congestion is observed on Tx Queues.
This patch enables Tx Queue congestion state check support.
If congested, try to resend the packet few times.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
NXP Copyright has been wrongly worded with '(c)' at various places.
This patch removes these extra characters. It also removes
"All rights reserved".
Only NXP copyright syntax is changed. Freescale copyright is not
modified.
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
rte_driver->name has the driver name and all physical and virtual
devices has access to it.
Previously it was not possible for virtual ethernet devices to access
rte_driver->name field (because eth_dev used to keep only pci_dev),
and it was required to save driver name in the device private struct.
After re-works on bus and vdev, it is possible for all bus types to
access rte_driver.
It is able to remove the driver name from ethdev device private data and
use eth_dev->device->driver->name.
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
Acked-by: Jan Blunck <jblunck@infradead.org>
Typically when the PMD issues a Rx command to DPAA2 hardware,
the HW writes the available descriptors into the given memory.
The RX function then processes the frames and prepare them as
mbufs.
This patch adds support to issue another pull request to hardware
in another memory location, before we start processing the output
of the first request. This help in controlling the CPU cycles
wasted during the wait for the hardware to write the descriptors.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The DPAA2 driver is not using the DPAA2 frame descriptor
software annotation area. This patch reduces the
PTA length to zero and adjust the RX Buffer Layout
accordingly.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
This code in device init is not required, as the buffer
layout setting is also being programmed during queue configuration.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
As the hardware determines which core will process which packet,
performance is boosted by direct cache warming/stashing as well
as by providing biasing for core-to-flow affinity, which ensures
that flow-specific data structures can remain in the core’s cache.
This patch enables the one cache line data stashing for packet
annotation data and packet context
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>