The Kunpeng930 DMA devices have the same PCI device id with Kunpeng920,
but with different PCI revision and register layout. This patch
introduces the basic initialization for Kunpeng930 DMA devices.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
The default mempool driver is one based on the rte_ring, and as such it
needs to be present to have just about any app (which doesn't override
the mempool) run. Given this state of affairs it is probably best to add
this default mempool driver to the always-enabled list to ensure we get
a runnable build in all cases. This means that, for example, to run some
NIC tests with testpmd in a minimal build, in most cases, all the user
should need to do is specify "-Denable_drivers=net/<nic_drv>" for the
build.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Add PMD parameter that allows one to select only subset of available
GPIOs.
This might be useful in cases where some GPIOs are already reserved yet
still available for userspace access but particular app should not touch
them.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Add support for custom interrupt handlers. Custom interrupt
handlers bypass kernel completely and are meant for fast
and low latency access to GPIO state.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Add initial support for PMD that allows to control particular pins form
userspace. Moreover PMD allows to attach custom interrupt handlers to
controllable GPIOs.
Main users of this PMD are dataplain applications requiring fast and low
latency access to pin state.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Improve vWQE and CQ Rx performance by tuning perfetches to 64B
cacheline size.
Also, prefetch the vWQE array offsets at cacheline boundaries.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Setting WAITW bit enables default min dequeue timeout of 1us.
Avoid the min dequeue timeout by setting WAITW only when dequeue_timeout
is configured.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Store and reuse workslot status for TT, GRP and HEAD status
instead of reading from GWC as reading from GWC imposes
additional latency.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support for allow or block list for devices bound
to the kernel driver.
When used the allow or block list applies as an additional
condition to the name prefix.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Kevin Laatz <kevin.laatz@intel.com>
Before registering the doorbell interrupt handler callback function,
all the valid doorbell bits within the NTB private data struct should
be cleared to avoid the confusion of the handshake timing sequence
diagram when setting up the NTB connection in back-to-back mode.
Fixes: 62012a7681 ("raw/ntb: add handshake process")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Adding useful debug prints in DPAA driver for
easy debugging. A devarg is added to enable various levels
of prints.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
This patch supports ordered queue for DPAA2 platform.
A devarg is added to enable strict ordering.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
This patch add more checks on next type for PDCP cases.
Fixes: 45e019608f ("crypto/dpaa2_sec: support integrity only PDCP")
Fixes: a1173d5559 ("crypto/dpaa_sec: support PDCP offload")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Few useful debug prints added in dequeue function.
These are controlled via pmd devargs. Details of using the
devarg is updated in dpaa2_sec.rst
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Add IV size and change the digest size to supported
value by the HW engine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
DPAA1 and DPAA2 platforms use SEC ERA 8 and 10 only.
Hence, code related to old SEC-ERA (1-7) is removed.
This patch removes code in SDAP and PDCP header related to these
ERA to simplify the codebase:
- Simplify logic using RTA_SEC_ERA_<> macro
- Remove era_2_sw_hfn_ovrd dedicated to RTA_SEC_ERA_2
Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Rather than using a session buffer that contains pointers to private
session data elsewhere, have a single session buffer.
This session is created for a driver ID, and the mempool element
contains space for the max session private data needed for any driver.
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Pending queue also need to be adjusted while updating the number of
descriptors.
Fixes: a455fd869c ("common/cnxk: align CPT queue depth to power of 2")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
CPT inflight request is used to track a request that is enqueued to
cryptodev. Having more than one inst use the same cacheline can result
in serialization of CPT result memory writes causing perf degradations.
Align inflight request to ROC cache line to ensure only one result would
be written per cache line..
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This patch fix the cipher params configuration in AEAD job if
QAT GEN4 unified cipher slice(UCS) enabled.
Fixes: 328d690d2f ("crypto/qat: update raw data path")
Cc: stable@dpdk.org
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Memory for ZUC cipher/auth key in session had to be expanded to 32 bytes,
instead of 16 bytes, when adding ZUC-256 support.
However, impact is low as this memory is part of a union
with bigger size than 32 bytes.
Coverity issue: 374374
Coverity issue: 374379
Fixes: 8c835018de ("crypto/ipsec_mb: support ZUC-256 for aesni_mb")
Cc: stable@dpdk.org
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
Multiple PMDs have dummy/noop Rx/Tx packet burst functions.
These dummy functions are very simple, introduce a common function in
the ethdev and update drivers to use it instead of each driver having
its own functions.
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Add promiscuous_enable, promiscuous_disable, allmulticast_enable,
and allmulticast_disable API stubs.
This helps clean up errors in dpdk-test link_bonding_mode4_autotest.
Signed-off-by: Robert Sanford <rsanford@akamai.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Tx command is prepared based on offloads enabled and stored in
Tx queue structure at tx_queue_setup phase.
In fastpath the command is copied from Tx queue to LMT line for
all the packets.
Since, the command contents are mostly constants we can move the
command preparation to fastpath and avoid accessing Tx queue
memory.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
lv_enabled is used to remember if large VF setting is configured, but
its value is not initialized at startup. This can lead to a different
configuration regarding the initial configuration of the PF.
For example, a first start is done with 8 rx and 8 tx queues. Large VF
is not needed and reta size is 64.
A second start is done with 20 rx and tx queues. Large VF is required
and reta size is 256.
A third start is done with 2 rx and tx queues. Large VF is not needed
but reta size is 256 as the PF has been configured during the second
start.
In order to have a consistent behavior regarding reta size whatever
the configuration of the PF (may be changed by a previous boot) the
lv_enabled must be set properly at the init phase.
Signed-off-by: Ghalem Boudour <ghalem.boudour@6wind.com>
Signed-off-by: Thibaut Collet <thibaut.collet@6wind.com>
Reviewed-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Ting Xu <ting.xu@intel.com>
