Tx command is prepared based on offloads enabled and stored in
Tx queue structure at tx_queue_setup phase.
In fastpath the command is copied from Tx queue to LMT line for
all the packets.
Since, the command contents are mostly constants we can move the
command preparation to fastpath and avoid accessing Tx queue
memory.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Functions like free, rte_free, and rte_mempool_free
already handle NULL pointer so the checks here are not necessary.
Remove redundant NULL pointer checks before free functions
found by nullfree.cocci
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Riverhead boards support spreading traffic across the
specified number of queues without using indirections.
This mode is provided by a dedicated RSS context type.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
On Riverhead boards, the client can control how many entries
to have in the indirection table of an exclusive RSS context.
Provide the new parameter to clients and indicate its bounds.
Extend the API for writing the table to have the flexibility.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
In the existing code, "n" is hardly a clear name for that.
Use a clearer name to help future maintainers of the code.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
On Riverhead boards, clients can query the limit on how many
queues an RSS context may address. Put the capability to use.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Remove the incomplete cplusplus guard in internal headers.
Fixes: 7525ebd8ebb0 ("common/mlx5: add glue functions on Windows")
Signed-off-by: Weiguo Li <liwg06@foxmail.com>
Meson 0.61.1 is giving warnings that the calls to run_command do not
always explicitly specify if the result is to be checked or not, i.e.
there is a missing "check" parameter. This is because the default
behaviour without the parameter is due to change in the future.
We can fix these warnings by explicitly adding into each call whether
the result should be checked by meson or not. This patch therefore
adds in "check: false" to each run_command call where the result is
being checked by the DPDK meson.build code afterwards, and adds in
"check: true" to any calls where the result is currently unchecked.
Bugzilla ID: 921
Cc: stable@dpdk.org
Reported-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Jerin Jacob <jerinj@marvell.com>
While probing the device with unsupported class, the process should
fail because no appropriate driver was found. After traversing all
the drivers, an error value should be returned for the case.
In the previous implementation, zero value indicating probing success
was wrongly returned.
Fixes: ad435d320473 ("common/mlx5: add bus-agnostic layer")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Memory region (MR) lookup by address inside mempool MRs
was not accounting for the upper bound of an MR.
For mempools covered by multiple MRs this could return
a wrong MR LKey, typically resulting in an unrecoverable
TxQ failure:
mlx5_net: Cannot change Tx QP state to INIT Invalid argument
Corresponding message from /var/log/dpdk_mlx5_port_X_txq_Y_index_Z*:
Unexpected CQE error syndrome 0x04 CQN = 128 SQN = 4848
wqe_counter = 0 wq_ci = 9 cq_ci = 122
This is likely to happen with --legacy-mem and IOVA-as-PA,
because EAL intentionally maps pages at non-adjacent PA
to non-adjacent VA in this mode, and MLX5 PMD works with VA.
Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities")
Cc: stable@dpdk.org
Reported-by: Wang Yunjian <wangyunjian@huawei.com>
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Updates nix_dump and npa_dump to use plt_dump function.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Improve inbound inline error handling for CN9K in terms of
packet delivered to application for different kinds of errors.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
An errata exists whereby, in certain cases NIX may use an
incorrect QINT_IDX for SQ interrupts. As a result, the
interrupt may not be delivered to software, or may not be
associated with the correct SQ.
When NIX uses an incorrect QINT_IDX :
1. NIX_LF_QINT(0..63)_CNT[COUNT] will be incremented for
incorrect QINT.
2. NIX_LF_QINT(0..63)_INT[INTR] will be set for incorrect
QINT.
Fixes: ae06070901ab ("common/cnxk: add NIX Tx queue management API")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
LF's error debug registers like NIX_LF_SQ_OP_ERR_DBG,
NIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug
info for an error detected during LMT operation or meta
enqueue or after meta enqueue granted respectively. HW
sets a valid bit when info is captured and SW is expected
to clear this valid bit by writing 1, else these registers
will show stale values of first interrupt when occurred and
will never update with subsequent interrupts.
Fixes: f6d567b03d28 ("common/cnxk: support NIX IRQ")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
In shaper profiles cleanup, Klockwork static analyzer tool reports
infinite loop although existing loop condition is alright.
False positive may be due to tqh_first not checked in loop,
hence switching to FOREACH_SAFE to make Klockwork happy.
Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE
register to be 24 instead of zero similar to other level SHAPE
registers. Also mask unused bits in adjust value.
Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Support matching existence of specific extension headers
after RTE_FLOW_ITEM_TYPE_IPV6 item.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Support matching existence of VLAN after
RTE_FLOW_ITEM_TYPE_ETH and RTE_FLOW_ITEM_TYPE_VLAN items.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Add ROC API for parsing custom pre_l2 headers as raw data.
Only relative offset is supported and search and limit is
not supported with this raw item type.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Reviewed-by: Satheesh Paul <psatheesh@marvell.com>
Adding changes to configure switch header type pre_l2 for cnxk.
pre_l2 headers are custom headers placed before the ethernet
header. Along with switch header type, user needs to provide the
offset within the custom header that holds the size of the
custom header and mask for the size within the size offset.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Reviewed-by: Satheesh Paul <psatheesh@marvell.com>
Update meter algorithm in NIX's band profile structure.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Acked-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adds roc APIs roc_nix_cq_head_tail_get(), roc_nix_sq_head_tail_get()
to get tail and head of receive and transmit queue respectively.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Use LMTST (Large atomic block store) burst as a performance optimization
when more than 15 pointers are requested to be freed.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
When multicast promiscuous was being enabled it caused the unicast
promiscuous to be disabled. This fix resolves this by setting
NIX_RX_MODE_PROMISC when eth_dev->data->promiscuous is set, regardless.
Fixes: 325d79c00a5a ("net/cnxk: support all multicast")
Cc: stable@dpdk.org
Signed-off-by: Asaf Ravid <aravid@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support for the imissed counter using the DevX API on Windows.
imissed is queried by creating a queue counter for the port, attaching
it to all created RQs and querying the "out_of_buffer" field.
If the counter cannot be created, imissed will always report 0.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The rte_kvargs_parse function parses the arguments
"key=value,key=value,..." string and return an allocated structure that
contains a key/value list.
It enables also to send a key without value and updates the values in
the following ways:
- "key=value,key,..." - value is updated as NULL.
- "key=value,key=,..." - value is updated as "" (empty string).
Mlx5 PMDs use this function to parse, but they don't support key without
value. They send the value as an argument to strtol function.
When strtol gets NULL as a parameter it cause a crash, when it gets ""
(empty string) it returns 0.
Adds a check that will prevent an argument in these formats, and returns
an error for it.
Fixes: 85209924039c ("common/mlx5: share memory related devargs")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The common drivers_probe function calls in a loop to all probe functions
for classes requested by the user. After it manages to probe them all,
it updates this on the device in the "classes_loaded" field.
If one of them fails, all those probed to it are remove using the
drivers_remove function. However, this function only releases the
classes in the "classes_loaded" field on the given device and misses the
newly probed classes.
This patch removes the condition from the release function, and ensures
that the caller function sends a more accurate parameter.
Fixes: 8a41f4deccc3 ("common/mlx5: introduce layer for multiple class drivers")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
ROC changes to support setting channel mask for SDP interfaces.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Wait for XAQ pool to get filled with the freed pointers
before proceeding.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Wait for SQB pool to get filled with the freed pointers
before proceeding.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add roc_npa_aura_op_available_wait() API which can be used to wait
until an NPA pool gets filled up to a certain count of pointers.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Use arch_extension instead of .cpu directive in NPA assembly code
snippets. Using .cpu directive with generic causes it to override
the micro architecture selected by march,mcpu.
For example if march=armv8.5-a+crypto+sve2 provided then the .cpu
directive overrides it to generic+crypto+sve2, use arch_extension
to get the expected result.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Before issuing the batch alloc, we clear the first word of
cache lines so that NPA can update the status. Make sure that
this line clear is flushed before the batch alloc is issued.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
When PLT_CACHE_LINE_SIZE is set to 64B, the memzone size reserved for
NPA stack could be a multiple of 64B. In such a case, when NDC SYNC
is initiated for the NPA LF, it could go and corrupt an additional
64B bytes as NDC flushes in multiples of ROC cache line size (128B).
So ensure that NPA stack size requested is a multiple of 128B.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Fix the order in which layer flags and layer type fields
are parsed when dumping the MCAM data.
Fixes: 9869c39918a0 ("common/cnxk: support flow entry dump")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Some devices have a WQE size limit for striding RQ. On some newer
devices, this limitation is smaller and information on its size is
provided by the firmware.
This patch adds the attribute query from firmware: the minimum required
size of WQE buffer for striding RQ in granularity of Bytes.
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
For cn9k, use HW GEN IV as default and add per pkt IV
in lookaside IPsec debug mode. Debug mode helps to verify
lookaside PMD using known outbound vectors in lookaside
autotest.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Print more info when command timeout happens. Print software and
hardware queue information.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
