Move all the individual driver fields allocation routines to one
routine - bnxt_drv_init(). This houses all such routines where
memory needs to be allocated once during the driver's lifetime
and does not need to be torn down during error recovery.
Rename some function names in accordance with their functionality.
bnxt_init_board() is doing nothing more than mapping the PCI bars,
so rename it as such.
Given that there is a bnxt_shutdown_nic that is called in dev_stop_op,
rename it's counterpart - bnxt_init_chip() that is called in
dev_start_op, to bnxt_start_nic. Also helps avoid confusion with some of
the other bnxt_init_xxx routines.
Rename bnxt_init_fw() to bnxt_get_config() as that is what that routine
is doing mostly functionality wise.
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Fix mask to include all four bits of hardware packet type
field.
Fixes: 97b1db288dd0 ("net/bnxt: use table based packet type translation")
Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Driver is not logging the complete FW version along with HSI version.
Fix it to indicate complete FW version string.
Fixes: 9a891c1764ea ("net/bnxt: update HWRM to version 1.9.2")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
In mlx4 PCI probing, there are some validations for the Ethernet device
configuration.
From each PCI device the function creates one or two Ethernet devices.
When one of validations fails during the creation of the second device,
the first device is not freed what caused a memory leak.
Free it.
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: David Marchand <david.marchand@redhat.com>
When mlx4 device is probed, 2 different ethdev ports may be created for
the 2 physical ports of the device.
Wrongly, when the device is removed, the created ports are not released.
Close and release the ethdev ports in remove process.
Bugzilla ID: 488
Fixes: 7fae69eeff13 ("mlx4: new poll mode driver")
Cc: stable@dpdk.org
Reported-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: David Marchand <david.marchand@redhat.com>
Currently, for a flow containing an age action, if flow is split to
sub-flows, a new age action will be created for each sub-flow.
However only the action created for the last sub-flow will be queried
on flow query and cleared on flow removal.
This behavior is wrong, causing a leak of resources.
Need to create just one action per flow, and use it for all sub-flows.
This patch adds the required check to make sure an age action is
created just once per flow, and used by all sub-flows.
Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Currently, for a flow containing a count action, if flow is split to
sub-flows, a new counter will be created for each sub-flow.
However only the counter created for the last sub-flow will be queried
on flow query and cleared on flow removal.
This behavior is wrong, causing a leak of resources.
Need to create just one counter per flow, and use it for all sub-flows.
This patch adds the required check to make sure a counter is
created just once per flow, and used by all sub-flows.
Fixes: fa2d01c87d2b ("net/mlx5: support flow aging")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Currently, the maximal flow priority in non-root table to user
is 4, it's not enough for user to do some flow match by priority,
such as LPM, for one IPV4 address, we need 32 priorities for each
bit of 32 mask length.
PMD will manage 3 sub-priorities per user priority according to L2,
L3 and L4. The internal priority is 16 bits, user can use priorities
from 0 - 21843.
Those enlarged flow priorities are only used for ingress or egress
flow groups greater than 0 and for any transfer flow group.
Signed-off-by: Dong Zhou <dongzhou@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
While there's the modify action and sample action with ratio=1
in the E-Switch flow, and modify action is after the sample
action, means that the modify should only impact on after sample.
MLX5 PMD will monitor the above case and split the E-Switch flow
into two sub flows, similar as sample flow did before:
- the prefix sub flow with all actions preceding the sample and the
sample action itself, also append the new jump action after sample
in the prefix sub flow;
- the suffix sub flow with the modify action and other actions
following the sample action.
The flow split as below:
Original flow: items / actions pre / sample / modify / actions sfx
prefix sub flow -
items / actions pre / set_tag action / sample / jump
suffix sub flow -
tag_item / modify / actions sfx
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The sampling feature introduces the scale flow group with factor,
then the scaled table value can be used for the normal path table
due to this table be created implicitly.
But if the input group value already be scaled, for example the
group value of sampling suffix flow, then use 'skip_scale" flag
to skip the scale twice in the translation action.
Consider the flow with jump action and this jump action could be
created implicitly, PMD may only scale the original flow group
value or scale the jump group value or both, so extend the
'skip_scale' flag to two bits:
If bit0 of 'skip_scale' flag is set to 1, then skip the scale the
original flow group;
If bit1 of 'skip_scale' flag is set to 1, then skip the scale the
jump flow group.
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
mlx5 E-Switch mirroring is implemented as multiple destination array in
one steering table. The array currently supports only port ID as
destination actions.
This patch adds the jump action support to the array as one of
destination.
The packets can be mirrored to the port and jump to the next table in
the same destination array allowing to continue handling in the new
table.
For example:
set sample_actions 0 port_id id 1 / end
flow create 0 ingress transfer pattern eth / end actions
sample ratio 1 index 0 / jump group 1 / end
flow create 1 ingress transfer group 1 pattern eth / end actions
set_mac_dst mac_addr 00:aa:bb:cc:dd:ee / port_id id 2 / end
The flow results all the matched ingress packets are mirrored
to port id 1 and go to group 1. In the group 1, packets are modified
with the destination mac and sent to port id 2.
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Update function mlx5_devx_cmd_query_hca_attr() to add the
reg_c_preserve bit query.
The stored metadata in register C may be lost in NIC Tx and
FDB egress while doing one of the following operations:
- packet encapsulation.
- packet mirroring (multiple processing paths).
- packet sampling (using Flow Sampler).
If the reg_c_preserve bit is set to 1, then the above
limitation is obsolete, the all metadata registers Cx
preserve their values even through the operations mentioned
above.
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add device ID support for family E823C, also update the base code
BSD version.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
In order to support configuring the device in Double VLAN Mode (DVM),
the DDP and FW have to support DVM. If both support DVM, the PF
that downloads the package needs to update the default recipes and set
the VLAN mode. This is done in ice_set_dvm().
In order to support updating the default recipes in DVM add support
for updating an existing switch recipe's lkup_idx and mask.
This is done by first calling the get recipe AQ (0x0292) with the
desired recipe ID. Then, if that is successful update one of the lookup
indices (lkup_idx) and its associated mask if the mask is valid
otherwise the already existing mask will be used.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Currently VLAN filters via RID4 are only based on VLAN ID. However, with
incoming support for Double VLAN Mode (DVM), the driver needs to be able
to support filtering on VLAN ID + VLAN TPID (i.e. 0x8100, 0x88a8, etc.).
Add support for this by adding two fields to the ice_fltr_info
structure. First, add the tpid_valid field so the code can determine
whether or not to overwrite the default 0x8100 value for programming
packets or use the tpid field.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Fix the wrong value of ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST
Fixes: 9ea028123a0b ("net/ice/base: align add VSI and update VSI AQ command buffer")
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
E1000_CTRL register should be updated according to fc_conf->mode's
value.
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
Since the VLAN offload virtchnl message name has been renamed to setting
style, the internal Ethernet type setting name needs be changed to avoid
confusing.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
In order to support enable/disable VLAN filtering the VF has to
negotiate the capability via VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2. If
VIRTCHNL_VLAN_TOGGLE is allowed for the VLAN filtering capabilities,
then there needs to be a method to allow this. Make the necessary
changes to support this.
Also, since the virtchnl_vlan_offload message has the desired format,
change the structure name to virtchnl_vlan_setting so it can be used for
VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 and
VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add eCPRI tunnel port add and rm ops to configure eCPRI UDP tunnel port
in "Device Config Function" (DCF).
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
When testpmd enabled the verbosity for the received packets, if two
packets were received at the same time, for example, sampling packet and
normal packet, the dump output of these packets may be overlapping due
to multiple core handling the multiple queues simultaneously.
The patch uses one string buffer that collects all the packet dump
output into this buffer and then printouts it at last, that guarantees
to printout separately the dump output per packet.
Fixes: d862c45b5955 ("app/testpmd: move dumping packets to a separate function")
Cc: stable@dpdk.org
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
The check-includes script allowed checking header files in a given
directory to ensure that each header compiled alone without requiring
any other header inclusions.
With header checking now being done by the chkincs app in the build
system this script can be removed.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
For CI builds, turn on the checking of includes.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Aaron Conole <aconole@redhat.com>
To verify that all DPDK headers are ok for inclusion directly in a C file,
and are not missing any other pre-requisite headers, we can auto-generate
for each header an empty C file that includes that header. Compiling these
files will throw errors if any header has unmet dependencies.
For some libraries, there may be some header files which are not for direct
inclusion, but rather are to be included via other header files. To allow
later checking of these files for missing includes, we separate out the
indirect include files from the direct ones.
To ensure ongoing compliance, we enable this build test as part of the
default x86 build in "test-meson-builds.sh".
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The rte_eventdev_pmd*.h files are for drivers only and should be private
to DPDK, and not installed for app use.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
The rte_ethdev_driver.h, rte_ethdev_vdev.h and rte_ethdev_pci.h files are
for drivers only and should be a private to DPDK and not installed.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Steven Webster <steven.webster@windriver.com>
The rte_rib6 header was using RTE_MIN macro from rte_common.h but not
including the header file.
Fixes: f7e861e21c46 ("rib: support IPv6")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>
The rte_power_guest_channel.h file did not include its dependent
headers, so add them.
Fixes: 5f443cc0f905 ("power: create guest channel public header file")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Clang does not have an "error" attribute for functions, so for marking
internal functions we need to check for the error attribute, and provide
a fallback if it is not present. For clang, we can use "diagnose_if"
attribute, similarly checking for its presence before use.
Fixes: fba5af82adc8 ("eal: add internal ABI tag definition")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
When key length is 0, zmalloc will return NULL pointer
and in that case it should not return NOMEM.
So in this patch, adding a check on key length.
Fixes: 8d1f3a5d751b ("crypto/dpaa2_sec: support crypto operation")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
During SA creation, if the required algorithm is not supported,
drivers can return ENOTSUP. But in most of the IPsec test cases,
if the SA creation does not success, it just returns
TEST_FAILED.
This patch fixes this issue by returning the actual return values
from the driver to the application, so that it can make decisions
whether the test case is passed, failed or unsupported.
Fixes: 05fe65eb66b2 ("test/ipsec: introduce functional test")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Add all the capabilities supported by the device.
Add the driver documentations.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
In order to support 32-bit systems, the 8B doorbell write should be
done by 2 4B stores.
The order between the store is important, that's why memory barrier
should be used between them.
The doorbell address is shared between all the queues, that's why a lock
should wrap the 2 stores.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add support for the next statistics operations:
- stats_get
- stats_reset
These statistics are counted by the SW data-path.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add implementation for the next compress data-path functions:
- dequeue_burst
- enqueue_burst
Add the next operation for starting \ stopping data-path:
- dev_stop
- dev_close
Each compress API enqueued operation is translated to a WQE.
Once WQE is done, the HW sends CQE to the CQ, when SW see the CQE the
operation will be updated and dequeued.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Mellanox user space drivers don't deal with physical addresses, that's
why any mbuf virtual address moved directly to the HW descriptor(WQE).
The mapping between the virtual address to the physical address is saved
in MR configured by the kernel to the HW.
Each MR has a key that should also be moved to the WQE by the SW.
When the SW see address which is not mapped, it extends the address
range and creates a MR using a system call.
Add memory region cache management:
- 2 level cache per queue-pair - no locks.
- 1 shared cache between all the queues using a lock.
Using this way, the MR key search per data-path address is optimized.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add support for the next operations:
- private_xform_create
- private_xform_free
The driver transformation structure includes preparations for the next
GGA WQE fields used by the enqueue function: opcode. compress specific
fields (window size, block size and dynamic size) checksum type and
compress type.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add support for the next operations:
- queue_pair_setup
- queue_pair_release
Create and initialize DevX SQ and CQ for each compress API queue-pair.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add a new compress PMD for Mellanox devices.
The MLX5 compress driver library provides support for Mellanox
BlueField 2 families of 25/50/100/200 Gb/s adapters.
GGAs (Generic Global Accelerators) are offload engines that can be used
to do memory to memory tasks on data.
These engines are part of the ARM complex of the BlueField 2 chip, and
as such they do not use NIC related resources (e.g. RX/TX bandwidth).
They do share the same PCI and memory bandwidth.
So, using the BlueField 2 device, the compress class operations can be
run in parallel to the net, vdpa, and regex class operations.
This driver is depending on rdma-core like the other mlx5 PMDs, also it
is going to use mlx5 DevX to create HW objects directly by the FW.
Add the probing functions, PCI bus connectivity, HW capabilities checks
and some basic objects preparations.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch fixes the missed digest in buffer support to
QAT symmetric raw API. Originally digest in buffer is
supported only for wireless algorithms
Fixes: 728c76b0e50f ("crypto/qat: support raw datapath API")
Cc: stable@dpdk.org
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
The python script introduced in this patch runs the crypto performance
test application for various test cases, and graphs the results.
Test cases are defined in config JSON files, this is where parameters
are specified for each test. Currently there are various test cases for
devices crypto_qat, crypto_aesni_mb and crypto_gcm. Tests for the
ptest types Throughput and Latency are supported for each.
The results of each test case are graphed and saved in PDFs (one PDF for
each test suite graph type, with all test cases).
The graphs output include various grouped barcharts for throughput
tests, and histogram and boxplot graphs are used for latency tests.
Documentation is added to outline the configuration and usage for the
script.
Usage:
A JSON config file must be specified when running the script,
"./dpdk-graph-crypto-perf <config_file>"
The script uses the installed app by default (from ninja install).
Alternatively we can pass path to app by
"-f <rel_path>/<build_dir>/app/dpdk-test-crypto-perf"
All device test suites are run by default.
Alternatively we can specify by adding arguments,
"-t latency" - to run latency test suite only
"-t throughput latency"
- to run both throughput and latency test suites
A directory can be specified for all output files,
or the script directory is used by default.
"-o <output_dir>"
To see the output from the dpdk-test-crypto-perf app,
use the verbose option "-v".
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
The csv output for each ptest type used ";" instead of ",".
This has now been fixed to use the comma format that is used in the csv
headers.
Fixes: f6cefe253cc8 ("app/crypto-perf: add range/list of sizes")
Fixes: 96dfeb609be1 ("app/crypto-perf: add new PMD benchmarking mode")
Fixes: da40ebd6d383 ("app/crypto-perf: display results in test runner")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
The csv output for the latency performance test had an extra header,
"Packet Size", which is a duplicate of "Buffer Size", and had no
corresponding value in the output. This is now removed.
Fixes: f6cefe253cc8 ("app/crypto-perf: add range/list of sizes")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
The symmetric session configure callback function in OCTEON TX2 crypto
PMD returns error if the cipher operation is not set to either encrypt
or decrypt. This patch sets the cipher operation for the null cipher
to encrypt.
Fixes: 74449375237f ("test/event_crypto_adapter: fix configuration")
Cc: stable@dpdk.org
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
For the wmb in order_process_stage_1 and order_process_stage_invalid in
the order test, they can be removed. This is because when the test results
are wrong, the worker core writes 'true' to t->err. Then other worker
cores, producer cores and the main core will load the 'error' index and
stop testing. So, for the worker cores, no other storing operation needs
to be guaranteed after this when errors happen.
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
