Commit Graph

731 Commits

Author SHA1 Message Date
Gordon Noonan
b5fcebb242 net/iavf: use write combining store for tail updates
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Gordon Noonan <gordon.noonan@intel.com>
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-06-10 12:04:16 +02:00
Andy Moreton
e27950a02b common/sfc_efx/base: add missing MCDI response length checks
Fixes: 6f619653b9 ("net/sfc/base: import MCDI implementation")
Fixes: e7cd430c86 ("net/sfc/base: import SFN7xxx family support")
Fixes: 94190e3543 ("net/sfc/base: import SFN8xxx family support")
Fixes: 34285fd089 ("common/sfc_efx/base: add match spec validate API")
Fixes: e61baa82e6 ("common/sfc_efx/base: add MAE action set provisioning APIs")
Fixes: b4fac34715 ("common/sfc_efx/base: add MAE action rule provisioning APIs")
Fixes: ed15d7f8e0 ("common/sfc_efx/base: validate and compare outer match specs")
Fixes: 7a673e1a4a ("common/sfc_efx/base: support outer rule provisioning")
Cc: stable@dpdk.org

Signed-off-by: Andy Moreton <amoreton@xilinx.com>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-05-19 11:32:49 +02:00
Andy Moreton
e1c9fcab3f common/sfc_efx/base: limit reported MCDI response length
MCDI helper routines in libefx include length checks for response
messages, to ensure that short replies and optional fields are
handled correctly.

If the MCDI response message from the firmware is larger than the
caller's buffer then the response length reported to the caller
should be limited to the buffer size. Otherwise length checks in
the caller may allow reading past the end of the buffer.

Fixes: 6f619653b9 ("net/sfc/base: import MCDI implementation")
Cc: stable@dpdk.org

Signed-off-by: Andy Moreton <amoreton@xilinx.com>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-05-19 11:32:49 +02:00
Stephen Hemminger
f0129207ec common/mlx5: add SPDX tag in Windows headers
These files were added without required SPDX headers.

Fixes: 7525ebd8eb ("common/mlx5: add glue functions on Windows")
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Tal Shnaiderman <talshn@nvidia.com>
2021-05-19 10:59:00 +02:00
Shiri Kuzin
9f39076b71 common/mlx5: fix mkey attributes initialization
The crypto driver added new fields to the mkey attributes struct:
crypto_en and set_remote_rw.

The entire mkey struct was not initialized, only specific fields in it,
which caused the new added fields not to be initialized resulting in a
mkey creation error.

This is fixed by initializing the entire mkey attributes struct to 0
which will prevent this issue from reoccurring if any fields are added
to the mkey struct in the future.

Fixes: 0111a74e13 ("common/mlx5: adjust DevX mkey fields for crypto")

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-09 09:06:31 +02:00
David Marchand
eeded2044a log: register with standardized names
Let's try to enforce the convention where most drivers use a pmd. logtype
with their class reflected in it, and libraries use a lib. logtype.

Introduce two new macros:
- RTE_LOG_REGISTER_DEFAULT can be used when a single logtype is
  used in a component. It is associated to the default name provided
  by the build system,
- RTE_LOG_REGISTER_SUFFIX can be used when multiple logtypes are used,
  and then the passed name is appended to the default name,

RTE_LOG_REGISTER is left untouched for existing external users
and for components that do not comply with the convention.

There is a new Meson variable log_prefix to adapt the default name
for baseband (pmd.bb.), bus (no pmd.) and mempool (no pmd.) classes.

Note: achieved with below commands + reverted change on net/bonding +
edits on crypto/virtio, compress/mlx5, regex/mlx5

$ git grep -l RTE_LOG_REGISTER drivers/ |
  while read file; do
    pattern=${file##drivers/};
    class=${pattern%%/*};
    pattern=${pattern#$class/};
    drv=${pattern%%/*};
    case "$class" in
      baseband) pattern=pmd.bb.$drv;;
      bus) pattern=bus.$drv;;
      mempool) pattern=mempool.$drv;;
      *) pattern=pmd.$class.$drv;;
    esac
    sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern',/RTE_LOG_REGISTER_DEFAULT(\1,/' $file;
    sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern'\.\(.*\),/RTE_LOG_REGISTER_SUFFIX(\1, \2,/' $file;
  done

$ git grep -l RTE_LOG_REGISTER lib/ |
  while read file; do
    pattern=${file##lib/};
    pattern=lib.${pattern%%/*};
    sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern',/RTE_LOG_REGISTER_DEFAULT(\1,/' $file;
    sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern'\.\(.*\),/RTE_LOG_REGISTER_SUFFIX(\1, \2,/' $file;
  done

Signed-off-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
2021-05-11 15:17:55 +02:00
Adam Dybkowski
cd218e52c4 common/qat: increase IM buffer size for GEN3
This patch increases the intermediate buffer size used for the
compression on QAT GEN3 to accommodate new hardware versions.

Fixes: a124830a6f ("compress/qat: enable dynamic huffman encoding")
Cc: stable@dpdk.org

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
2021-05-05 16:45:19 +02:00
Bing Zhao
8207e84b21 common/mlx5: add DevX connection tracking objects creation
Adding support for connection tracking ASO creation via Devx command.
Right now only bulk creation is supported.

By default, the objects with zero contents will be created. Before
using a single object, the modification via posting a WQE to the ASO
CT SQ is needed.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-05-05 14:30:12 +02:00
Bing Zhao
0c6285b727 common/mlx5: check connection tracking offload capability
During startup, the ASO connection tracking offload capability could
be queried via HCA_CAP_QUERY command. If the HW doesn't support ASO
CT, the value would be 0 by default. The following initialization
should be skipped and the creation of the CT object should return
a failure directly.

The following CT creation should also check this capability. With
the old driver, the pre-processing macro should be used in order to
make the compiling pass.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-05-05 14:30:10 +02:00
Bing Zhao
dc4e9e820f common/mlx5: add connection tracking object
The structures of ASO connection tracking offload object are added
based on the definitions in the PRM. One CT object context will be
loaded into the cache completely in a reversed order of dwords. The
valid bit should be the MSB of the last dword. This is used for the
conntrack context creation and update, as well as for the query.

The capabilities 2 (HCA_CAP_2) layout is also added. The connection
tracking related capabilities could be queried via the HCA_CAP_2.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-05-05 14:30:08 +02:00
Michael Baum
cd414f81d1 net/mlx5: workaround ASO memory region creation
Due to kernel issue in direct MKEY creation using the DevX API for
physical memory, this patch replaces the ASO MR creation to use Verbs
API.

Fixes: f935ed4b64 ("net/mlx5: support flow hit action for aging")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-03 09:09:50 +02:00
Ting Xu
cfacca202f common/iavf: fix order of protocol header types
The new virtchnl protocol header types for IPv4 and IPv6 fragment are
not added in order, which will break ABI. Move them to the end of the
list.

Fixes: e6a42fd915 ("common/iavf: add protocol header for IP fragment")
Cc: stable@dpdk.org

Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-04-30 15:11:13 +02:00
Gregory Etelson
0f250a4b6e common/mlx5: add PRM definitions for integrity check
Add integrity and IPv4 IHL bits to PRM file.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-05-04 17:37:22 +02:00
Tal Shnaiderman
11e61a9467 common/mlx5: read checksum capability from DevX
mlx5 in Windows needs the hca capability csum_cap
to query the NIC for checksum offloading support.

Added the capability as part of the capabilities
queried by the PMD using DevX.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Odi Assli <odia@nvidia.com>
2021-04-28 11:16:46 +02:00
Li Zhang
aa065a9cf3 net/mlx5: support meter PPS profile
Currently meter algorithms only supports bytes units for meter profiles.
Using ASO feature, the driver can support metering in per packet units.

Add support for packet units in meter profiles.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-04-27 14:27:08 +02:00
Qi Zhang
7880d1d4ef common/iavf: use macro to define offload/capability
Currently raw hex values are used to define specific bits for each
offload/capability in virtchnl.h. The can and has led to duplicate
defined bits. Fix this by using the BIT() macro so it's
immediately obvious which bits are used/available.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2021-04-26 10:17:50 +02:00
Qi Zhang
e53176ef4b common/iavf: refine comment in virtual channel
General clean up for comment in virtchnl.

Signed-off-by: Sridhar Samudrala <sridhar.samudrala@intel.com>
Signed-off-by: Joshua Hay <joshua.a.hay@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2021-04-26 10:17:29 +02:00
Qi Zhang
8265d39a73 common/iavf: add enumeration for Rx descriptor ID
Support for allowing VFs to negotiate the descriptor format was added
previously.

This support requires that the VF specify which descriptor format to use
when requesting Rx queues. The VF is supposed to request the set of
supported formats via the new VIRTCHNL_OP_GET_SUPPORTED_RXDIDS, and then
set one of the supported formats in the rxdid field of the
virtchnl_rxq_info structure.

The virtchnl.h header does not provide an enumeration of the format
values. The existing implementations in the PF directly use the values
from the DDP package.

Make the formats explicit by defining an enumeration of the RXDIDs.
Provide an enumeration for the values as well as the bit positions as
returned by the supported_rxdids data from the
VIRTCHNL_OP_GET_SUPPORTED_RXDIDS.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2021-04-26 10:12:06 +02:00
Qi Zhang
44a87aa9c2 common/iavf: fix duplicated offload bit
The value of offload VIRTCHNL_VF_OFFLOAD_CRC bit already existed as
VIRTCHNL_VF_CAP_ADV_LINK_SPEED. Fix this now by changing the value of
VIRTCHNL_VF_OFFLOAD_CRC to a currently unused value.

Also, move the define for VIRTCHNL_VF_CAP_ADV_LINK_SPEED in the correct
place to line up with the other bit values and add a comment for its
purpose. Hopefully this will prevent from defining duplicate bits moving
forward.

Fixes: e244eeafce ("net/iavf/base: update virtual channel")
Cc: stable@dpdk.org

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2021-04-26 10:10:19 +02:00
Ting Xu
c5ed57d1ba common/iavf: add header types for PPP and L2TPv2
Added two virtchnl protocol header types for L2TPv2 and PPP to support
the RSS hash for PPPoL2TPv2oUDP.

Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-04-25 04:16:01 +02:00
Hongbo Zheng
3de9af2aaa common/sfc_efx/base: fix dereferencing null pointer
In function efx_pci_xilinx_cap_tbl_find, pointer entry_offsetp is used
before null pointer check, which may cause access to null pointer.

This patch fix this problem.

Fixes: ba9568b8b4 ("common/sfc_efx/base: add Xilinx capabilities table lookup")
Cc: stable@dpdk.org

Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2021-04-27 17:21:33 +02:00
Pavan Nikhilesh
b5a52c9d97 event/cnxk: add event port and queue xstats
Add support for retrieving statistics from SSO HWS and HWGRP.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2021-05-04 07:06:53 +02:00
Pavan Nikhilesh
5787cf0cbb common/cnxk: update inline asm prefix
Update inline asm prefix to prevent overriding cpu type, instead express
the additional extensions required.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2021-05-04 04:53:03 +02:00
Pavan Nikhilesh
da54e60991 common/cnxk: rename deprecated PCI constant
The PCI_ANY_ID constant is deprecated and renamed as RTE_PCI_ANY_ID.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2021-05-04 04:45:53 +02:00
Suanming Mou
caec80f92a common/mlx5: add UMR and RDMA write WQE definitions
This patch adds the struct defining UMR and RDMA write WQEs.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:51:18 +02:00
Dekel Peled
1a2d8c3ffe common/mlx5: support DevX register write access
This patch adds support of write operation to NIC registers.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:37 +02:00
Dekel Peled
f85e9a395d common/mlx5: add crypto register structs and definitions
Encryption key management requires use of several related registers.
This patch adds the relevant structs and values, according to PRM
definitions.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:37 +02:00
Dekel Peled
abda4fd9bb common/mlx5: support general object credential
CREDENTIAL object is used for any crypto operation in wrapped mode.

This patch add support of CREDENTIAL object create operation.
Add reading of CREDENTIAL support capability.
Add function to create general object type CREDENTIAL, using DevX API.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:37 +02:00
Shiri Kuzin
c31f3f7f7b common/mlx5: share Verbs device match function
The get_ib_device_match function iterates over the list of ib devices
returned by the get_device_list glue function and returns the ib device
matching the provided address.

Since this function is in use by several drivers, in this patch we
share the function in common part.

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:37 +02:00
Shiri Kuzin
25245d5dc9 common/mlx5: share hash list tool
In order to use the hash list defined in net in other drivers, the
hash list is moved to common utilities.

In addition, the log definition was moved from the common utilities to
a dedicated new log file in common in order to prevent a conflict.

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:37 +02:00
Dekel Peled
d5ee804d04 common/mlx5: add crypto BSF struct and definitions
This patch adds the struct defining crypto BSF segment of UMR WQE,
and the related value definitions and offsets.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:49:31 +02:00
Dekel Peled
38e4780b25 common/mlx5: support general object crypto login
CRYPTO_LOGIN Object is used to login to the device as crypto user
or crypto officer.
Required in order to perform any crypto related control operations.

This patch adds support of CRYPTO_LOGIN object create operation.
Add reading of CRYPTO_LOGIN support capability.
Add function to create general object type CRYPTO_LOGIN, using DevX API.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:42:24 +02:00
Dekel Peled
21ca2494ac common/mlx5: support general object KEK import
IMPORT_KEK object is used to wrap (encrypt) critical security
parameters, such as other keys and credentials, when those need
to be passed between the device and the software.

This patch add support of IMPORT_KEK object create operation.
Add reading of IMPORT_KEK support capability.
Add function to create general object type IMPORT_KEK, using DevX API.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:47 +02:00
Dekel Peled
0111a74e13 common/mlx5: adjust DevX mkey fields for crypto
MKEY that will be used for crypto purposes must be created with
crypto_en and remote access attributes.
This patch adds support for them in the DevX MKEY context.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:45 +02:00
Dekel Peled
178d8c506e common/mlx5: support general object DEK
Data Encryption Keys (DEKs) are the keys used for data
encryption/decryption operations.

Add reading of DEK support capability.
Add function to create general object type DEK, using DevX API.

Arrange common version.map file in alphabetical order.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:41 +02:00
Dekel Peled
f7d1f11ced common/mlx5: add HCA capabilities for AES-XTS crypto
Update the PRM structure and HCA capabilities reading, to include
relevant capabilities for AES-XTS crypto.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:39 +02:00
Dekel Peled
876d4702b1 common/mlx5: optimize read of general capabilities
General object types support is indicated in bitmap general_obj_types,
which is part of HCA capabilities list.
Currently this bitmap is read multiple times, and each time a different
bit is extracted.

This patch optimizes the code, reading the bitmap once into a local
variable, and then extracting the required bits.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:38 +02:00
Dekel Peled
753a7c08e2 common/mlx5: rename GENEVE TLV option object
Rename MLX5_OBJ_TYPE_GENEVE_TLV_OPT as
MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT, to align with other general
objects names.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:34 +02:00
Dekel Peled
97dcf0567e common/mlx5: remove redundant spaces in PRM header
File drivers/common/mlx5/mlx5_prm.h includes structs representing
data items as defined in PRM document.
Some of these structs were copied as-is from kernel file mlx5_ifc.h.
As result the structs are not all aligned with the same spacing.

This patch removes redundant spaces and new lines from several structs,
to align all structs in mlx5_prm.h to the same format.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-05-04 22:41:32 +02:00
Bruce Richardson
7d5cfaa750 build: fix formatting of Meson lists
Running "./devtools/check-meson.py --fix" on the DPDK repo fixes a
number of issues with whitespace and formatting of files:

* indentation of lists
* missing trailing commas on final list element
* multiple list entries per line when list is not all single-line

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-05-04 15:01:47 +02:00
Li Zhang
894711d3fe common/mlx5: create ASO flow meter object with DevX
Add DevX API to create ASO flow meter object.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-04-21 08:28:00 +02:00
Li Zhang
5b9e24ae14 common/mlx5: add read ASO flow meter HCA capability
Read and store the device capability of FLOW_METER_ASO general object,
using the DevX API.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-04-21 08:27:56 +02:00
Li Zhang
49e0ccb547 common/mlx5: add definitions for ASO flow meter
This patch adds different PRM definitions, related to
ASO (Advanced Steering Operation) flow meter feature,
in MLX5 PMD code.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-04-21 08:27:54 +02:00
Shun Hao
21091aba4e common/mlx5: add color register idle bits definition
8 bits are used for meter color in meter register. When the meter
register can be shared, the rest 24 bits can be used by others.
This adds the definition for the 24 bits that can be shared.

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-04-21 08:27:44 +02:00
Robin Zhang
e9c5672ac1 net/iavf: deprecate i40evf PMD
The i40evf PMD will be deprecated, iavf will be the only VF driver for
Intel 700 serial (i40e) NIC family.

To reach this, there will be 2 steps:

Step 1: iavf will be the default VF driver, while i40evf still can be
selected by devarg: "driver=i40evf".
This is covered by this patch, which include:
1) add all 700 serial NIC VF device ID into iavf PMD
2) skip probe if devargs contain "driver=i40evf" in iavf
3) continue probe if devargs contain "driver=i40evf" in i40evf

Step 2: i40evf and related devarg are removed, this will happen at DPDK
21.11

Between step 1 and step 2, no new feature will be added into i40evf
except bug fix.

Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2021-04-19 10:36:17 +02:00
Haifei Luo
a38d22ed45 common/mlx5: add functions for single flow dump
Add mlx5 APIs for single flow dump feature

Signed-off-by: Haifei Luo <haifeil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-04-19 12:45:02 +02:00
Chengwen Feng
611c394c18 common/dpaax: fix possible null pointer access
This patch fixes possible null pointer access when dump iova table.

Fixes: 2f3d633aa5 ("common/dpaax: add library for PA/VA translation table")
Cc: stable@dpdk.org

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2021-04-21 16:58:34 +02:00
Bruce Richardson
99a2dd955f lib: remove librte_ prefix from directory names
There is no reason for the DPDK libraries to all have 'librte_' prefix on
the directory names. This prefix makes the directory names longer and also
makes it awkward to add features referring to individual libraries in the
build - should the lib names be specified with or without the prefix.
Therefore, we can just remove the library prefix and use the library's
unique name as the directory name, i.e. 'eal' rather than 'librte_eal'

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-04-21 14:04:09 +02:00
Bruce Richardson
4ad4b20a79 drivers: change indentation in build files
Switch from using tabs to 4 spaces for meson.build indentation.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-04-21 14:04:09 +02:00
Bruce Richardson
cf995efc53 drivers: clean up build lists
Ensure all lists of drivers are standardized:
* one driver per line
* lists double-indented with spaces (as they are line continuations)
* elements in alphabetical order
* opening and closing list brackets "[" & "]" on own lines
* last element has trailing comma

Any code snippets in the list files is adjusted to single-indent using
whitespace to correspond to the new style also.

The lists of standard library dependencies per class, and other short
lists are not formatted one-per-line as these lists are not expected to
grow beyond 2 or 3 entries.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-04-21 12:37:55 +02:00