The space in descriptor buffer is scarce as it is limited to
64 words for platforms except ERA10 (which has 128).
As the descriptors are processed with QI, it adds some words
to the descriptor which is passed.
Some descriptors used for SDAP were using too much words reaching
the limit.
This patch reduces the number of words used by removing the inlining
of some keys (done for performance) in order to have working
descriptors.
Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
For SDAP, we are not using the protocol operation to perform
4G/LTE operation so the DPOVRD option is not used.
Removing it save some space in the descriptor buffer and
execution time.
Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The offset of the HFN word and Bearer/Dir word is different
depending on type of PDB.
The wrong value was used.
This patch address this issue
Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This patch adds support for AES_CMAC integrity
in non-security mode.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
add DES-CBC support and enable available cipher-only
test cases.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The rte_cryptodev_pmd.* files are for drivers only and should be
private to DPDK, and not installed for app use.
Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The API rte_cryptodev_pmd_is_valid_dev, can be used
by the application as well as PMD to check whether
the device is valid or not. Hence, _pmd is removed
from the API.
The applications and drivers which use this API are
also updated.
Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Update min tailroom to reflect IPsec additions.
PMD crypto_cn9k & crypto_cn10k would have packet
grow into tailroom post IPsec processing.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
When given a source length 0 for CCM, the encryption and decryption
functions did not call the EVP_ENCRYPTUPDATE/EVP_DECRYPTUPDATE functions
with a src and dst, causing some FIPS validation failures for testcases
with PLen=0:
process_openssl_auth_encryption_ccm() line 1131:
Process openssl auth encryption ccm failed
Fixes: 1a4998dc4d ("crypto/openssl: support AES-CCM")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Submit two instructions with one LMTST operation.
Also updated dequeue path to have local var for constants.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Swap is not required for ZUC. Update IV updation
sequence to remove the redundant swap in case of ZUC.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The opcode for encryption & decryption is the
same and single routine would be able to handle
both encryption and decryption operations.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Add support for ZUC API change in ucode 1.13
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.
The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.
Fixes: 6152534e21 ("crypto/mlx5: support queue pairs operations")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Added flow control based check to determine CPT IQ is full.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Added a common macro to set eventdev enqueue and
dequeue operations to reduce code.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
CPT can be told to submit events to SSO upon completion.
Crypto adapter uses this feature and the new flag can be
used to optimize receive path in those cases.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Use otx2_mbox_memcpy() instead of memcpy() to prevent unaligned access.
Fixes: a0645ed0d6 ("crypto/octeontx2: discover capabilities")
Cc: stable@dpdk.org
Signed-off-by: Danny Patel <dannyp@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
The QP setup function allocates buffer for its
opaque MR and register it into MR structure.
After buffer allocation and before MR registration,
it tries allocate MR Btree.
When the MR Btree allocation fails, the buffer was
not freed what caused a memory leak.
Allocate the MR Btree before buffer alloction.
Fixes: 0165bccdb4 ("compress/mlx5: add memory region management")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
IPsec verify functions can be made common which can
be used for both cn9k and cn10k
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Adding functions for hash generation that can be used
in hmac opad/ipad calculation.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
For device probe and iterator, devargs name was key information,
parsed by rte_devargs_parse. In legacy parser, devargs name was
extracted after bus name:
bus:name,kv_arguments,,,
Example:
pci:83:00.0,arguments,...
vdev:pcap0,...
To be compatible with legacy parser, this patch introduces new
bus driver API devargs_parse to parse devargs and update devargs name.
If devargs_parse not implemented by bus driver, the new syntax parser
rte_devargs_layers_parse default will resolve devargs name from bus's
"name" argument.
Different bus driver might choose different keys from arguments with
unified format. The PCI bus implementation fills the devargs name with
the "addr" argument, example:
-a bus=pci,addr=83:00.0/class=eth/driver=mlx5,...
name: 0000:03:00.0
-a bus=vdev,name=pcap0/class=eth/driver=pcap,...
name:pcap0
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Gaetan Rivet <grive@u256.net>
During port stop/start sequence the Thor FW is returning an error.
This is because we are deriving incorrect active Rx ring and using
that wrong information in the bnxt_vnic_rss_cfg HWRM command.
Fix it by using the rx_queue_state from eth_dev.
Fixes: 0105ea1296 ("net/bnxt: support runtime queue setup")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
On chips like Thor, port stop/start sequence could result in a crash
in the application. This is because of false detection of a bad
opaque in the Rx completion and the subsequent kicking-in of the ring
reset code to recover from the condition.
The root cause being that the port stop/start would result in the HW
starting with fresh values, while the driver internal tracker variable
`rx_next_cons` is still pointing to a stale value.
Fix this by resetting rx_next_cons to 0 in bnxt_init_one_rx_ring()
Fixes: 03c8f2fe11 ("net/bnxt: detect bad opaque in Rx completion")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
The GENEVE TLV option matching is done using a flex parser.
Recent update in firmware, requires that in order to match on the
GENEVE TLV option the "geneve_tlv_option_0_exist" bit should be set.
Add the new "geneve_tlv_option_0_exist" setting when translating the
GENEVE TLV option item.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
A Rx ring stop start sequence may result in the FW returning
a different set of Rx ring and AGG ring IDs. If the ring group
is not updated with the new IDs, the HW sees the host driver using
incorrect BD types for the Rx ring and AGG ring. This can cause
the chip to go into a bad state or encounter RE_flush issue
or leak mbufs in the HW.
Fix this by issuing a bnxt_hwrm_ring_grp_free() and an
bnxt_hwrm_ring_grp_alloc() to refresh the ring group information.
Fixes: 9b63c6fd70 ("net/bnxt: support Rx/Tx queue start/stop")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
When an ETH or VLAN flow item directly preceding ECPRI (i. e. a pattern
for eCPRI over Ethernet) did not specify the eCPRI protocol, matches
were not restricted to eCPRI traffic. For example, "eth / ecpri / end"
pattern behaved as "eth / end". Implicitly add Ethernet type condition,
so that "eth / ecpri / end" behaves as "eth type is 0xAEFE / end".
Fixes: daa38a8924 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
A core dump is being generated with the following call stack:
0 _mm256_storeu_si256 (__A=..., __P=0x80)
1 rte_mov32 (src=0x2299c9140 "", dst=0x80)
2 rte_memcpy_aligned (n=60, src=0x2299c9140, dst=0x80)
3 rte_memcpy (n=60, src=0x2299c9140, dst=0x80)
4 mprq_buf_to_pkt (strd_cnt=1, strd_idx=0, buf=0x2299c8a00, len=60,
pkt=0x18345f0c0, rxq=0x18345ef40)
5 rxq_copy_mprq_mbuf_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=5)
6 rxq_burst_mprq_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=46,
err=0x7f76e0ff6a28, no_cq=0x7f76e0ff6a27)
7 mlx5_rx_burst_mprq_vec (dpdk_rxq=0x18345ef40, pkts=0x7f76e0ff6a88,
pkts_n=128)
8 rte_eth_rx_burst (nb_pkts=128, rx_pkts=0x7f76e0ff6a88,
queue_id=<optimized out>, port_id=<optimized out>)
This crash is caused by an attempt to copy previously uncompressed CQEs
into non-allocated mbufs. There is a check to make sure we only use
allocated mbufs in the rxq_burst_mprq_v() function, but it is done only
before the main processing loop. Leftovers of compressed CQEs session are
handled before that loop and may lead to the mbufs overflow as seen.
Move the check for replenished mbufs up to protect uncompressed CQEs
session leftovers from accessing non-allocated mbufs after the
mlx5_rx_mprq_replenish_bulk_mbuf() function is invoked.
Bugzilla ID: 746
Fixes: 0f20acbf5e ("net/mlx5: implement vectorized MPRQ burst")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The RSS expansion algorithm is using a graph to find the possible
expansion paths. The VLAN item in the flow pattern requires special
treatment, because it should not be added implicitly by the expansion
algorithm. If the flow pattern ends with ETH item, the pattern will be
expanded with IPv4 and IPv6.
For example:
testpmd> flow create ... eth / end actions rss / end
ETH END
ETH IPV4 END
ETH IPV6 END
If a VLAN item follows the ETH item in the flow pattern, the pattern
will be expanded with IPv4 and IPv6 following the VLAN item.
For example:
testpmd> flow create ... eth / vlan / end actions rss level 1 / end
ETH VLAN END
ETH VLAN IPV4 END
ETH VLAN IPV6 END
The case of inner tunnel VLAN item was not taken care of so the flow
pattern did not expand with IPv6 and IPv4 as expected.
Example with inner VLAN:
testpmd> flow create ... / vxlan / eth / vlan / end actions rss level 2
/ end
The current result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
The expected result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
ETH IPV6 UDP VXLAN ETH VLAN IPV4 END
ETH IPV6 UDP VXLAN ETH VLAN IPV6 END
The fix is to introduce a new flag to set on a graph expansion node
to apply the 'explicit' behavior, meaning the node is not added to
the expanded pattern, if it is not found in the flow pattern, but the
expansion alg can go deeper to its next nodes.
Fixes: c7870bfe09 ("ethdev: move RSS expansion code to mlx5 driver")
Cc: stable@dpdk.org
Signed-off-by: Lior Margalit <lmargalit@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Remove bit reverse for TCP/UDP port mask, since it causes the flows with
some TCP/UDP ports to disobey the flow director rules.
Fixes: ea230dda16 ("net/txgbe: configure flow director filter")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
