Commit Graph

286 Commits

Author SHA1 Message Date
Qi Zhang
8c1c61f970 net/ice/base: update profile to recipe bitmap array
Correctly update profile to recipe bitmap array after adding and
associating recipes. This fixes an issue where determining unused
recipe result index slots was incorrect.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
9b6f0c969b net/ice/base: add GENEVE offset
Add Geneve offset for tunneled packets to allow dummy packets to be
properly created.

Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
c5adb3c448 net/ice/base: enable RSS with ether layer for PPPoE
Add these two ptype(MAC_PPPOD_PAY and MAC_PPPOE_PAY) in outer mac
bitmap, so it can hash for outer mac.

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
661264d19f net/ice/base: remove Rx flex descriptor programming
Removing Rx flex descriptor metadata and flag programming from the code,
these registers cannot be written to as they are read only.
The programming for all fields per RxDID is now handled differently.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
f4f79aa849 net/ice/base: add AQC get link topology handle support
Add AQC get link topology handle support. This is needed to determine
Direct Attach (DA) or backplane media type for PHY types that support
either. Get link topology handle cage node type request can be used to
determine if a cage is present or not. If a cage is present for PHY
types that supports both DA and backplane media type, then the media
type is DA, else the media type is backplane.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
fc882012b3 net/ice/base: delay less
Shorten the delay for SQ responses, but increase the number of loops.
Max delay time is unchanged, but some operations complete much more
quickly.

In the process, add a new define to make the delay count and delay time
more explicit, and simplify the code so it's the same for both switch
and NIC mode. Add comments to make things more explicit.

Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
82f3e28d23 net/ice/base: replace open-code duplication
Use BIT_ULL() instead of ICE_FLOW_HASH_FLD() which does the same bit shift
operation.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
8b4cd4eda0 net/ice/base: update to register definition file
Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
6632c0556d net/ice/base: correct abbreviations
Correct abbreviation issues found by running abbrevcheck.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
e123d30f4a net/ice/base: remove unnecessary if branch
We are already in the branch "if (fm_list->vsi_count == 1)"
no need to exit and re-enter.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
dbe449e5dc net/ice/base: remove unnecessary dummy packet finding
We don't need to find a dummy packet when removing a rule so remove
the call to get the dummy packet. This also obviates some variables
so remove them also.

Also reduce the scope of rule_buf_sz.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
c3d6ac02c0 net/ice/base: update switch training packets with open ports
This patch updates UDP tunneled training packets with an appropriate
UDP dest port. For the correct profile to be chosen, an open tunnel
port must be included in the training packet.

Added GENEVE tunnel labels in the test package in order to test GENEVE
tunnel rule creation.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
c932653c36 net/ice/base: maximize switch recipe words per line
Remove grouping rules to maximize the number of words placed into
a recipe line. This will allow more recipes to be added by reducing
the number of result indices required.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
58f116731d net/ice/base: refactor removal of VLAN promiscuous rules
Currently ice_clear_vsi_promisc() detects if the VLAN ID sent is not 0
and sets the recipe_id to ICE_SW_LKUP_PROMISC_VLAN in that case and
ICE_SW_LKUP_PROMISC if the VLAN_ID is 0. However this doesn't allow VLAN
0 promiscuous rules to be removed, but they can be added. Fix this by
checking if the promisc_mask contains ICE_PROMISC_VLAN_RX or
ICE_PROMISC_VLAN_TX. This change was made to match what is being done
for ice_set_vsi_promisc().

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
21b28a9ef7 net/ice/base: fix flag settings in AQ call
Removed setting Read flag in the Get Allocated Resource Descriptors AQ
command (0x020A). The read flag is not required for this command and
causes the FW to return an error.

Fixes: d781ccbdd1 ("net/ice/base: add functions to get allocated resources")
Cc: stable@dpdk.org

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
b32be950a3 net/ice/base: remove unnecessary conditional check
There is no reason to do this conditional check before the assignment so
simply remove it.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
2aaf1d1b67 net/ice/base: add RSS support for PPPoE and GTPU
Added RSS support for PPPoE with inner TCP and UDP.
Added RSS support for GTPU with IPv4 and IPv6.

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
b7d34ccc47 net/ice/base: packet encapsulation for RSS
RSS configurations calls currently support only non-tunneled packets,
which uses outer-first IPs. Adding another call to configure RSS for
tunneled packets which will enable hashing on inner-last IP. RSS hash
will only be done on the innermost IP.
- Update RSS configuration calls to take packet segment count as input
  argument
- Update flow profile ID to include identifier for encapsulated packet
  [0:31] : Packet match fields
  [32:62]: Protocol header header
  [63]: Encapsulation flag, 0 if non-tunneled, 1 if tunneled

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
12f6ea93f0 net/ice/base: fix for RSS hash on inner UDP port
Before this patch, only outer IP with inner UDP port can appear in
RSS hash, because the extraction sequence uses outer IP protocol
ID with Inner UDP protocol ID. ICE_PROT_UDP_OF always extracts the
TUNNELED UDP port values (i.e., 4789 for VXLAN). ICE_PROT_UDP_IL_OR_S
will extract NON-TUNNELED UDP port or inner UDP port.

Fixes: aa1cd410fa ("net/ice/base: add flow module")
Cc: stable@dpdk.org

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
282bd7d78d net/ice/base: consolidate packet type group
This patch is an optimization to decrease the number of TCAM entries
used in the profile blocks, especially for RSS. To be most effective
this will also require a package change in order to decrease the number
of PTYPE groups necessary to program RSS, FD and ACL rules.

Change required package version to 1.3.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
56c0ab4405 net/ice/base: add routine for tunnel port query
Add ice_get_open_tunnel_port routine, which can be used to find
an open tunnel port for creating switch and flow director training
packets.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
f636f2888c net/ice/base: move and add some help function and macros
The patch move ice_ilog2 and ice_is_pow2 to ice_type.h, also add help
macro ROUND_UP and IS_ETHER_ADDR_EQUAL.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
eda40e22b8 net/ice/base: improve switch chained recipe
When updating switch database with chained recipes from
firmware, where a null pointer derefence was occurring due to looking
into a sub-recipe entry which is not filled in.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
8b6e6e4024 net/ice/base: update UDP tunnel switch training packets
Change UDP tunnel training packets for the switch to work for both
Geneve and VXLAN cases.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
aa6ff47ad8 net/ice/base: return switch error on invalid match criteria
Modify ice_add_adv_rule to return an error when an invalid match
criteria is requested by the caller. This happens when the protocol
and offset pair is not supported by the package.

This change required a fix for the offset in the VXLAN GPE header,
and also found an issue with NVGRE where the package does not seem
to extract the correct offsets.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
55744222e6 net/ice/base: associate recipes by profile type
Change recipe to profile association logic to determine the profile type
to determine if a profile is compatible with the rule being added.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
54f75a4ce2 net/ice/base: support not locking sideband queue
For certain PTP clock adjustments, there is a use case for locking the
sideband queue at a higher level and performing an atomic series of
operations while the sideband queue is locked.  To accommodate this use
case, split ice_sw_send_cmd() into a version that takes the lock and a
version that does not.

Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
d1880ece7d net/ice/base: add function to configure Tx AQ command
This function is needed by the driver to move PSM leaf nodes to a new
parent.

Additionally, add struct ice_aqc_move_txqs to struct ice_aq_desc so
driver code can access it.

Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
5f9c389466 net/ice/base: initialize driver NVM data earlier
The driver detects and warns about FW rollback mode before getting the NVM
version (through ice_init_nvm) which results in "0.00 0x0 0.0.0" being
printed. Fix this by calling ice_init_nvm earlier.

This could have been fixed by moving ice_print_rollback_msg as well, but
it made more sense to move ice_init_nvm closer to the flow that gets the
FW version information (i.e. control queue init flow).

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
381bd0f265 net/ice/base: set status when global cfg lock is unavailable
To download the DDP file to the device, a PF first has to grab the
global configuration lock. When a PF can't grab this lock, set
hw->pkg_dwnld_status to ICE_AQ_RC_EEXIST.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
3b326f5945 net/ice/base: add more opcode and macros
Add more opcode and macros:

1. Add opcode for the NVM Update EMPR command.
2. Add opcode for NVM save factory settings
3. Add opcode for NVM Write/Write Activate calls
4. Add loopback reporting to get link response macros
5. Add link event defines macros

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
7b6b3886de net/ice/base: update flag bits
Currently the VLAN ice_flg64_bits are off by 1. Fix this by
setting the ICE_FLG_EVLAN_x8100 flag to 14, which also updates
ICE_FLG_EVLAN_x9100 to 15 and ICE_FLG_VLAN_x8100 to 16.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
a6d7b12cab net/ice/base: add 32-byte Flex Rx descriptor
Add 32-byte Flex RX Descriptor structure definition.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
2ebf458473 net/ice/base: add 16-byte Flex Rx descriptor
Add 16-byte Flex RX descriptor structure definition.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
7bfb7c6468 net/ice/base: move function declaration
Improve code orgnization, move declaration of ice_cfg_tc_nod_bw_alloc and
ice_cfg_rl_burst_size from ice_common.h to ice_nvm.h.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
18a6dd5222 net/ice/base: improve switch advanced rule
Correct algorithm to detect free field vector indexes to be
used for recipe line result values. The code now scans all
recipes that are associated with all the field vector being
targed for a new recipe to detect which result indexes are
unused.

Change recipe chaining code to place recipe on a single line
if it will fit, rather than looking to break things apart
according to preferred combinations.

These improvements fix a condition where recipes were getting
added with conflicting result index values.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
ca9a2c6974 net/ice/base: add locks for flow functions
Wrap functions to search for flow profiles, add and remove RSS
configurations with flow profile locks. This is to ensure that if
several VFs and PFs are disabled at the same time functions that access
the flow profile lists are thread safe.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
d1c2f76b44 net/ice/base: support GTP and PPPoE protocols
Added switch protocol segments for both GTP and PPPOE protocols.
Added RSS protocol segments for both GTP and PPPOE protocols.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
f035feb474 net/ice/base: support NVM access commands
Add a new structure, ice_nvm_access, used to request access to read or
write certain NVM related registers.

The structure is used by NVM Update to request read or write of specific
NVM registers in order to perform updates.

Additionally, there is a command to request the driver "features"
structure which represents data about what features of the NVM access
interface the driver supports.

Implement ice_handle_nvm_access to parse the access request and perform
the necessary function.

This function verifies that the access request is valid. If so, the
function will delegate to perform the register read, register write, or
copying of the driver ice_nvm_features structure.

If the request is invalid, the function will report a suitable error
codition that can be propagated out.

Only a subset of registers is accessible, and all other registers will
be rejected with ICE_ERR_OUT_OF_RANGE.

When reading, the contents of the variable sized data buffer will be
used as storage for returning the register value. When writing, the
contents will be used as input for the value to write to the register.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
b06499a433 net/ice/base: update Boot Configuration Section read of NVM
Boot Configuration Section Block has been moved to the
Preserved Field Area (PFA) of NVM. So, this patch updates
the NVM reads that involve Boot Configuration Section.

Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
07c417e5fc net/ice/base: fix overrun
Added boundary check for layer_num in function ice_sched_rm_rl_profile,
and ice_sched_add_rl_profile.

Cc: stable@dpdk.org

Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
807331f3ef net/ice/base: fix type-mismatch
The iterators are u8, but the values being compared against are u16s.
It may not ever be the case that the comparison is against a value
larger than the upper bound of the smaller type, but code analysis tools
don't know that.

Fixes: 93e84b1bfc ("net/ice/base: add basic Tx scheduler")
Cc: stable@dpdk.org

Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
a823afa55f net/ice/base: check root pointer for validity
ice_sched_get_tc_node uses pi->root without checking for NULL. Add a
check to prevent NULL pointer dereference.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
348ea028ea net/ice/base: fix memory leak
Need to free new ice_vsig_prof if no valid ptype can be found.

Fixes: d935fb5bb0 ("net/ice/base: fix packet type size")
Cc: stable@dpdk.org

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
2db7c617f6 net/ice/base: resolve static analysis issues
Coverity complains first_free can be -1 resulting in a negative shift left
when k equals 0; i.e. the expression 1 << (first_free - k). Fix this by
explicitly checking for this case.

Cc: stable@dpdk.org

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
9467486f17 net/ice/base: enable masking for RSS and FD field vectors
Allow masking per word field on RSS and FD field vectors.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
37e960435c net/ice/base: move VSI to VSI group
Add function to add a VSI to a given VSIG and update package with this
entry. The usual flow in XLT management would iterate through all
characteristics of the input VSI and create a new VSIG and TCAMs till a
matching characteristic is found. When a match is found the VSI is moved
into a matching VSIG and entries are collapsed, leading to added package
update calls. This function serves as an optimization if we know
beforehand that the input VSI has characteristics same as VSI configured
previously added to a VSIG. This is particularly useful for VF VSIs
which are all usually programmed with the same configurations.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
7e5778f880 net/ice/base: add NVM pkg flag
Add flag for case where active package has been loaded from NVM.

Signed-off-by: Ashish Shah <ashish.n.shah@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
99c1bd25bd net/ice/base: adjust DCB INIT for SW mode
Adjust ice_init_dcb to set the is_sw_lldp boolean
in the case where the FW has been detected to be
in an untenable state such that the driver
should forcibly make sure it is off.

This will ensure that the FW is in a known state.

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
0f11bdc08f net/ice/base: support reading REPC statistics
The GLV_REPC register contains statistics for tracking received packets
that are discarded due to certain errors.

This register behaves differently from some of the other related
statistics registers in two ways. First, it contains two 16bit
statistics, and thus cannot be read as a 32bit or 40bit statistic.

Second, the two stats do not roll over, but instead cap at 0xFFFF.

Add a new ice_stat_update_repc function which will read the register and
increment the appropriate statistics in the ice_eth_stats structure.

Since the register does not roll over, make use of the "Write Clear"
behavior, and write to the register to reset it every time we read it.

Add extra space for the two statistics that are counted by this
register, rx_errors, and rx_no_desc.

For now, wrap the new function and stats counters in !LINUX_SUPPORT.
This can later be removed if and when the Linux driver implements
support for reading the statistics.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00