Test app for lookaside IPsec is added with
AES-CBC-HMAC-SHA256 test cases.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Extend IPsec lookaside test framework to support chained
operations and add AES-CBC 128 known vector tests.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Downcasting a void * to struct aesni_gcm_session * caused the session
data to be treated as tainted.
Removing the void * temporary variable and adding a cast avoids this
issue.
Coverity issue: 374377
Fixes: 746825e5c0 ("crypto/ipsec_mb: move aesni_gcm PMD")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
The qp was being used in the cleanup without checking if it was non NULL.
A check is now added to verify qp is non NULL before use.
Coverity issue: 374375
Fixes: c75542ae42 ("crypto/ipsec_mb: introduce IPsec_mb framework")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
When setting up a qp in a secondary process, the local qp pointer is set
to the stored device qp, configured by the primary process for that
device, but only if that device qp is not NULL.
If the device qp was not set up correctly by the primary process and has
a NULL value, the local qp variable stays at the default initialised
value, NULL. This causes a NULL pointer dereference later in the
function when using the qp value.
This is fixed by always setting the local qp to the value of the device
qp stored, and then checking if qp is NULL, returning an error if it is.
Coverity issue: 374382
Fixes: 72a169278a ("crypto/ipsec_mb: support multi-process")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Update microcode completion code handling to update the required mbuf &
crypto op flags. IP checksum good case is now reported by specific
microcode completion code.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
For cn9k, use HW GEN IV as default and add per pkt IV
in lookaside IPsec debug mode. Debug mode helps to verify
lookaside PMD using known outbound vectors in lookaside
autotest.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
If the packet size to be incremented after IPsec processing is less
than size of hdr (size incremented before submitting), then extend_tail
can become negative. Allow negative values for the variable.
Fixes: 67a87e8956 ("crypto/cnxk: add cn9k lookaside IPsec datapath")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Print more info when command timeout happens. Print software and
hardware queue information.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The memory would be updated by hardware. Use atomics to read the same.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Inflight count calculation is updated to cover wrap around cases where
head can become smaller than tail.
Fixes: fd390896f4 ("crypto/cnxk: allow different cores in pending queue")
Cc: stable@dpdk.org
Reported-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Verification doesn't cover cases when NULL auth/cipher is provided as a
chain. Removed the separate function for verification and added a
replacement function which calls the appropriate downstream functions.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Adding context reload in datapath for IV in debug mode.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Add skip for transport mode tests that are not supported. Also,
updated the transport mode path to configure IP version as v4.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
CTX writes only require the lengths are 8B aligned. Use the struct size
directly.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
CPT CTX write with microcode would require CPT flush to complete to have
DRAM updated with the SA. Since datapath requires SA direction field,
introduce a new flag for the same.
Session destroy path is also updated to clear sa.valid bit using CTX
reload operation.
Session is updated with marker to differentiate s/w immutable and s/w
mutable portions.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Update the macro to include newly added ciphers.
Updated the functions populating caps to throw error
when max is exceeded.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Clear session data before populating fields to not have garbage data.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Copy DF/DSCP fields would get set based on ipsec_xform in the code
preceding this. Setting it again would cause the options to be reset.
Fixes: 78d03027f2 ("common/cnxk: add IPsec common code")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
MISC CPT instruction behaves differently based on minor opcode.
Define the missing minor opcodes for MISC major opcode.
Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Use the XAQ AURA create and free API while initializing the
inline device.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Due to an errata writing to vWQE flush register might hang NIX.
Add workaround for vWQE flush hang by waiting for the max
coalescing timeout to flush out any pending vWQEs.
Fixes: ee48f711f3 ("common/cnxk: support NIX inline inbound and outbound setup")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch introduces new api for retrieving event port id
of eth rx adapter.
Signed-off-by: Naga Harish K S V <s.v.naga.harish.k@intel.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
While dequeuing the packets from the event device, burst size
is provided in the API. This was not getting properly
configured in the application. This patch correctly configures
the burst size.
Fixes: aaf58cb85b ("examples/l3fwd: add event port and queue setup")
Cc: stable@dpdk.org
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Sunil Kumar Kori <skori@marvell.com>
Add external clock support for cnxk timer adapter.
External clock mapping is as follows:
RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK1 = TIM_CLK_SRC_GPIO,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK2 = TIM_CLK_SRC_PTP,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK3 = TIM_CLK_SRC_SYNCE,
TIM supports clock input from external GPIO, PTP, SYNCE clocks.
Input resolution is adjusted based on CNTVCT frequency for better
estimation.
Since TIM is unaware of input clock frequency, application is
expected to pass the frequency.
Example:
-a 0002:0e:00.0,tim_eclk_freq=122880000-0-0
The order of frequencies above is GPIO-PTP-SYNCE.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Minimum supported interval should now be retrieved from
mailbox based on the clock source and clock frequency.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
When event delivery is through internal port, stats are maintained
by HW and we should avoid reading SW data structures for stats.
Fix missing internal port checks.
Fixes: 995b150c1a ("eventdev/eth_rx: add queue stats API")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Number of direct credits, atomic inflight and history list are
updated to DLB2.0 supported sizes. As DLB2.0 does not provide
dev arg to override the default per-queue atomic inflight
allocation, it is removed from the documentation.
Fixes: f3cad285bb ("event/dlb2: add infos get and configure")
Cc: stable@dpdk.org
Signed-off-by: Rashmi Shetty <rashmi.shetty@intel.com>
Reviewed-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
While debugging running DPDK service in a container, it is
useful to see which file creation failed. Don't hide this
failure with DEBUG.
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Some drivers currently have their own checks and give some non
consistent reasons when an internal dependency is unavailable.
drivers/meson.build also checks for internal dependencies via 'deps'.
Let's rely on it for consistency, and smaller code.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Long Li <longli@microsoft.com>
