GCC build with '-O0' failed for:
../drivers/net/igc/base/igc_api.c
Assembler messages:
29: Error: selected processor does not support `casp x0,x1,x2,x3,[x4]'
82: Error: selected processor does not support `caspa x0,x1,x2,x3,[x4]'
135: Error: selected processor does not support `caspl x0,x1,x2,x3,[x4]'
188: Error: selected processor does not support `caspal x0,x1,x2,x3,[x4]'
This is due to c_args not been passed to meson.
Fixes: 8cb7c57d9b3c ("net/igc: support device initialization")
Cc: stable@dpdk.org
Reported-by: Feifei Wang <feifei.wang2@arm.com>
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Tested-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Haiyue Wang <haiyue.wang@intel.com>
Remove the operation of optical modules in the link function, because
when device binds from dpdk to kernel, it will be linked failed. This
function does not take effect in cable mode, therefore, optimization
is required.
Fixes: 54ac33869932 ("net/hinic: set link down and up")
Cc: stable@dpdk.org
Signed-off-by: Guoyang Zhou <zhouguoyang@huawei.com>
The maximum number of queues on the chip can be any value greater
than 0, it does not have to be the power of two, if it does not be
fixed, dpdk initialization may be failed with OVS mode firmware.
Fixes: 828d3e15a9dc ("net/hinic/base: support context and work queue")
Cc: stable@dpdk.org
Signed-off-by: Guoyang Zhou <zhouguoyang@huawei.com>
In the function rte_flow_shared_action_destroy(),
the errno ETOOMANYREFS has been replaced with EBUSY in the
commit dc328d1c555a ("ethdev: rename a flow shared action error code").
Another occurrence of ETOOMANYREFS, added later by mistake,
is replaced with EBUSY errno.
Fixes: fa7ad49e96b5 ("net/mlx5: fix shared RSS action update")
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Tal Shnaiderman <talshn@nvidia.com>
Tested-by: Tal Shnaiderman <talshn@nvidia.com>
PMD did not remove tunnel offload object from tunnels database before
it released the object memory. As the result, the tunnels database
become corrupted and subsequent search operations triggered PMD crash.
The patch removes tunnel offload object from the tunnels database when
the object is not in-use by PMD any more.
Fixes: bc1d90a3cf6f ("net/mlx5: fix build with Direct Verbs disabled")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
In mlx5 internal hash list tool, there is a log print when an entry
allocation is failed: Can't allocate hash list entry.
Some initialization checks triggers hash list registration in order to
check some capabilities. Here, the failure in registration doesn't
lead to failure in the initialization flow, that is why the log level
can be lower.
Move the entry allocation failure log to debug level.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Reviewed-by: Asaf Penso <asafp@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Invalid memory release order of DevX resources caused PMD crash.
1. SQ and CQ memory must be unregistered with DevX before it is freed.
2. SQ objects reference to a CQ ones. Hence, SQ should be destroyed in
advance of CQ it references to.
Fixes: 6deb19e1b2d2 ("net/mlx5: separate Rx queue object creations")
Fixes: 88f2e3f18cc7 ("net/mlx5: rearrange SQ and CQ creation in DevX module")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The rte_flow_item_vlan items are refined.
The structs do not exactly represent the packet bits captured on the
wire anymore so should only copy real header instead of the whole struct.
Replace the rte_flow_item_* with the existing corresponding rte_*_hdr.
Fixes: 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
&device requires the %u format specifer not the %d specifier, as
&device is unsigned.
Fixes: a46bbb57605b ("net/bnxt: update multi device design")
Cc: stable@dpdk.org
Signed-off-by: Conor Walsh <conor.walsh@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Representor is a port in DPDK that is connected to a VF in such a way
that assuming there are no offload flows, each packet that is sent
from the VF will be received by the corresponding representor. While
each packet that is sent to a representor will be received by the VF.
This is very useful in case of SRIOV mode, where the first packet that
is sent by the VF will be received by the DPDK application which will
decide if this flow should be offloaded to the E-Switch.
Representor shares interrupts handler with host PF over the PCI
address. Therefore, after PF completes its interrupts handler
initialization, no additional actions required for representor.
Fixes: 26c08b979d26 ("net/mlx5: add port representor awareness")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The shared RSS action update was not operational due to lack
of kernel driver support of TIR object modification.
This commit introduces the workaround to support shared RSS
action modify using an indirect queue table update instead of
touching TIR object directly.
Limitations: the only supported RSS property to update is queues, the
rest of the properties ignored.
Fixes: d2046c09aa64 ("net/mlx5: support shared action for RSS")
Signed-off-by: Andrey Vesnovaty <andreyv@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
If user don't set the dv_xmeta_en to 1 or 2,
in the flow_dv_convert_action_set_meta function:
- flow_dv_get_metadata_reg may return the REG_NONE,
when MLX5_METADATA_FDB enabled for metadata set action.
- reg_to_field(REG_NONE) returns MLX5_MODI_OUT_NONE,
that is invalid and rdma-core fails.
The rdma-core calltrace:
dr_action_create_modify_action
dr_actions_convert_modify_header
dr_action_modify_sw_to_hw
dr_action_modify_sw_to_hw_set
dr_ste_get_modify_hdr_hw_field
Fixes: fcc8d2f716fd ("net/mlx5: extend flow metadata support")
Cc: stable@dpdk.org
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Changing the allocation scheme to improve mbufs locality caused mbufs
overrun in some cases. Revert the previous replenish logic back.
Calculate a number of unused mbufs and replenish max this number of mbufs.
Mark the last 4 mbufs as fake mbufs to prevent overflowing into consumed
mbufs in the future. Keep the consumed index and the produced index 4 mbufs
apart for this purpose.
Replenish some mbufs only in case the consumed index is within the
replenish threshold of the produced index in order to retain the cache
locality for the vectorized MPRQ routine.
Fixes: 5c68764377 ("net/mlx5: improve vectorized MPRQ descriptors locality")
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
mlx5 PMD refuses to update link state if link speed is defined but
status is down or if link speed is undefined but status is up, even if
the ioctl() succeeded.
This prevents application to detect link up/down event, especially when
the link speed is not correctly detected.
Commit [1] allowed returning unknown link speed, so now PMD allows
the return of unknown link speed in the above case.
Due to some old kernel driver bug, link speed wasn't detected properly.
[1] http://git.dpdk.org/dpdk/commit/?id=810b17d116f03
Signed-off-by: Benoît Ganne <bganne@cisco.com>
Signed-off-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The rte_flow_item_eth and rte_flow_item_vlan items were updated in [1].
The rte_flow_item_ipv6 item was updated in [2].
The structs now contain additional metadata following the header data.
The size to use for match should be the header data size only, and
not the size of the whole struct.
This patch replaces the rte_flow_item_* with the corresponding rte_*_hdr.
Fixes: 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
Fixes: ad976bd40d28 ("ethdev: add extensions attributes to IPv6 item")
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
The rte_flow_item_eth and rte_flow_item_vlan items are refined.
The structs do not exactly represent the packet bits captured on the
wire anymore.
Should use real header instead of the whole struct.
Replace the rte_flow_item_* with the existing corresponding rte_*_hdr.
Fixes: 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
Fixes: f9210259cac7 ("net/mlx5: fix raw encap/decap limit")
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The rte_flow_item_eth and rte_flow_item_vlan items are refined.
The structs do not exactly represent the packet bits captured on the
wire anymore so should only copy real header instead of the whole struct.
Replace the rte_flow_item_* with the existing corresponding rte_*_hdr.
Fixes: 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
In regex QP setup, the PMD creates some SQ objects.
When SQ object creation is failed, the previous SQ objects memory were
not freed what caused a memory leak.
Free them.
Fixes: 54fa1f6a67d7 ("regex/mlx5: add teardown for fastpath buffers")
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The constant representing the size of the metadata is defined as a
regular number (32-bit signed), even though all of its uses request an
unsigned int variable.
Similarly the constant representing the maximal output is also defined
as a regular number, even though all of its uses request an unsigned int
variable.
Change the type of the above constants to unsigned.
Fixes: 5f41b66d12cd ("regex/mlx5: setup fast path")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
During the rules flush, the rxp_poll_csr_for_value function is called
twice. The rxp_poll_csr_for_value function can fail for two reasons:
1. It could not read the value from register, in which case the
function returns -1.
2. It read a value, but not the value it expected to receive. In this
case it returns -EBUSY.
When the function fails it prints an error message that is relevant only
for a second type of failure. Moreover, for failure of the first type it
prints a value of an uninitialized variable.
In case of success, the function prints a debug message about the number
of cycles it took. This line was probably copied by mistake, since the
variable it reads from, is always equal to 0 and is not an indicator of
the number of cycles.
Remove the incorrect line about the cycles, and reduce the error print
only for the relevant error.
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The rxp_flush_rules function tries to read and write to the register
several times using DevX API, and when it fails the function returns an
error.
Similarly the rxp_init_eng function also tries to write to the register
several times, and if writing is failed, it returns an error too.
Both functions have one write that the function does not check if it
succeeded, overriding the return value from the write function without
using it.
Add a check for this writing, and return an error in case of failure.
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Fixes: e3dbbf718ebc ("regex/mlx5: support configuration")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The rxp_poll_csr_for_value function defines a variable named ret. It is
the return value of the function, and it is updated to 0 by default
later in the function.
Similarly the rxp_init_rtru function also defines a variable named ret.
The function assigns into it return values from functions during the
function.
In both functions they initialize the ret variable when defining it.
however, in both cases they do not use any ret variable before assigning
into them different values, so the initializations are unnecessary.
Clean the aforementioned unnecessary initializations.
Fixes: e3dbbf718ebc ("regex/mlx5: support configuration")
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The mlx5_regex_rules_db_import function goes over all engines in the
loop and program rxp rules.
The iterator of the loop is called id and the variable representing the
number of engines is called priv->nb_engines.
The id variable is of uint8_t type while the priv->nb_engines variable
is of uint32_t type. The size of the priv->nb_engines variable is much
larger than the number of iterations allowed by the id type.
Theoretically there may be a situation where the value of the
priv->nb_engines will be greater than can be represented by 8 bits and
the loop will never end.
Change the type of id to uint32_t.
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The mlx5_regex_pci_probe function allocates a mlx5_regex_priv structure
using rte_zmalloc.
If the allocation fails, the function jumps to the dev_error label in
order to release previously allocated resources in the function.
However, in the dev_error label it attempts to refer to the internal
fields of the priv structure and if its allocation fails (as in this
case) it is actually dereferencing to NULL.
Replace the jump with an error label.
Fixes: 1db6ebd4ef58 ("regex/mlx5: fix crash on initialization failure")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
The function rte_zmalloc() could return NULL, the return value
need to be checked.
Fixes: dc49e6aa4879 ("compress/isal: add ISA-L compression functionality")
Fixes: 7bf4f0630af6 ("compress/isal: add ISA-L decomp functionality")
Cc: stable@dpdk.org
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Lee Daly <lee.daly@intel.com>
Unlinking queues from port should be done during port release. Doing it
during device re-configuration could result in segfault as ports array
is re-allocated based on new number of ports.
Fixes: f7ac8b66b23c ("event/octeontx2: support linking queues to ports")
Cc: stable@dpdk.org
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Fix unconditional Tx flush, in case of Tx only we need to check if
work slot is non-empty before issuing flush.
Also, in packet retransmit cases added check for the reference
count and flush the work slot only for the last packet.
Fixes: cb7ee83b6365 ("event/octeontx2: improve single flow performance")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Since selftest now depends on dynamic mbuf fields it is not
feasible to run selftest on device probe.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Since selftest now depends on dynamic mbuf fields it is not
feasible to run selftest on device probe.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
For kupeng 930, there are 3 registers to control the enable
status of a TQP(i.e. task queue pair, include a txq and a rxq).
One of them controls whether the TQP is enabled, and the other
two controls whether the rxq and txq are enabled. The registers
used to control the enabled status of the rxq and txq are enabled
by default. Therefore, after the TQP is enabled, the rxq and txq
are enabled by default.
Currently, when the number of rxq is not equal to the number of txq, the
unused rxqs or txqs are not disabled by driver, so these unused queues
will be enabled in this situation. And the related HW rings have not
been initialized which could lead to a hardware exception.
This patch fix it by disable these unused queues during enable the TQPs.
Fixes: fa29fe45a7b4 ("net/hns3: support queue start and stop")
Cc: stable@dpdk.org
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
The HW and SW DCB configurations need to be updated only
after the DCB configuration information changed. But the
change of tx/rx queue number is ignored. If user decreases
the number of tx queue after configuring multi-TC, the queue
mapping information in hns3_tc_queue_info can not be updated.
And then accessing the released queue resource in
"hns3_init_tx_ring_tc" will trigger a segment fault.
Fixes: 62e3ccc2b94c ("net/hns3: support flow control")
Cc: stable@dpdk.org
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
In the experimental function rte_flow_shared_action_destroy()
introduced in DPDK 20.11, the errno ETOOMANYREFS was used.
This errno is not always available on Windows,
so it is preferred using EBUSY instead.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Tal Shnaiderman <talshn@nvidia.com>
Tested-by: Tal Shnaiderman <talshn@nvidia.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
The 'nic_io' memory is set to NULL before it is freed, this is wrong,
and the freeing of some private port resources should be moved from the
".remove(device)" function to the ".dev_close(port)" function.
Fixes: f30e69b41f94 ("ethdev: add device flag to bypass auto-filled queue xstats")
Cc: stable@dpdk.org
Signed-off-by: Guoyang Zhou <zhouguoyang@huawei.com>
Existing code uses the previous API offered by rdma-core in order
to create ASO Flow Hit action.
A general API is now formally released, to create ASO action of any
type. This patch moves the MLX5 PMD code to use the formal API.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Existing code uses the hard-coded value REG_C_5 as input for function
mlx5dv_dr_action_create_flow_hit().
This patch updates function mlx5_flow_get_reg_id() to return the
selected REG_C value for ASO Flow Hit operation.
The returned value is used, after reducing offset REG_C_0, as input
for function mlx5dv_dr_action_create_flow_hit().
Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Recent patch introduced the use of ASO flow hit action for age action.
The relevant management struct uses dynamically allocated memory.
This memory was not freed on closing.
This patch adds memory freeing as needed.
Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Starting ConnectX-6 Dx, the VF device ID is generic
and not per chip.
https://pci-ids.ucw.cz/v2.2/pci.ids
101e ConnectX Family mlx5Gen Virtual Function
This means that all will have the same VF device ID.
Fixes: 5fc66630bed5 ("net/mlx5: add ConnectX6-DX device ID")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Tunnel offload API provides applications with ability to restore
packet outer headers after partial offload. Exact feature execution
depends on hardware abilities and PMD implementation. Hardware that is
supported by MLX5 PMD places a mark on a packet after partial offload.
PMD decodes that mark and provides application with required
information.
Application can call the restore API for packets that are part of
offloaded tunnel and not. It's up to a PMD to provide correct
information.
Current MLX5 tunnel offload implementation does not allow applications
to use flow MARK actions. It is restricted to tunnel offload use only.
This fault was triggered by application that did not activate tunnel
offload and called the restore API with a marked packet. The PMD tried
to decode the mark value and crashed. The patch decodes mark value
only if tunnel offload is active.
Fixes: 4ec6360de37d ("net/mlx5: implement tunnel offload")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
When creating a flow with eCPRI item, the mask and the value are both
needed in order to build the matching criteria.
In the current implementation, the unused value bits clear operation
was missed when filling the mask and value fields. For the value, the
bits not required were not masked with the mask provided. Indeed,
this action is not mandatory. But when creating a flow in the root
table, the kernel driver got involved and a check would prevent this
flow from being created. The same flow could be created successfully
with the userspace rdma-core on the non-root tables.
An AND operation needs to be added to clear the unused bits in the
value when building the matching criteria. Then the same flow can be
created successfully no matter with kernel driver or with rdma-core.
Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The sample and mirror action objects are maintained on the list
shared between the ports belonging to the same multiport Infiniband
device(between representors).
The actions in the NIC steering domains might contain the references
to the sub-flow action objects created over the given port. The action
deletion might happen in the context of the different port and on the
deletion of referenced objects the incorrect port might be specified.
To avoid this we should save the port on what the sub-flow actions
were created and then use this saved port for sub-flow action release.
This commit saves the create device in the sample and mirror actions
struct to avoid using the incorrect port device in releasing.
Fixes: 19784141692e ("net/mlx5: make sample and mirror action thread safe")
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Reviewed-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Currently, header reformat action uses the hash list 32-bit key
generated in header reformat register function directly. The key will
not be recalculated in the hash list function.
As the 64-bit key is composed of the 32-bit attributes and 32-bit
reformat buffer csum, the hash list function only gets 32-bit key
directly will take the attribute part only, csum part will be ignored.
For different header reformat actions, the attributes can be the same,
while the buffer will be different. Only take the attribute part causes
lots of the conflicts.
This commits adds the attribute part and the significant different csum
part for the key.
Fixes: f961fd490fd4 ("net/mlx5: make header reformat action thread safe")
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The MLX5_ENCAPSULATION_DECISION_SIZE constant is used
to check the raw encap/decap actions for the raw header
size. The header is constructed of the rte_xxx_hdr
structures instead of rte items. Hence, constant
must be defined with rte_xxx_hdr structure sizes.
Fixes: 50f576d657d7 ("net/mlx5: fix VLAN actions in meter")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>
When the representor device was set to PF1 in bonding mode, iterating
device iterator that looking for representors by bonding device failed
to match PF0 pci address with PF1 address. So detaching PF bonding
device only detached all representors on PF0.
This patch registers all representors of PF1 with PF0 as PCI device.
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The following assertion fails in case RTE_ENABLE_ASSERT is enabled:
PANIC in mlx5_tx_handle_completion():
assert "(txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16)
== cqe->wqe_counter" failed
The free completion queue only contains an expected WQE counter if
RTE_LIBRTE_MLX5_DEBUG is enabled as well. Thus enabling
RTE_ENABLE_ASSERT alone causes the assert to fail.
Compile the assert conditionally only if RTE_ENABLE_ASSERT is enabled.
Fixes: 0afacb04f506 ("common/mlx5: remove NDEBUG")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The kernel can use two approaches to distinguish the E-Switch
source vport in the packet metadata - either with dedicated
source_port field or register C0. To eliminate the extra source
vport matching in the hardware the source_port field can be
set to specific values (0xFFFF) for the wire source port.
This match can be applied to recognize wire port only in FDB
domain. Missing the register C0 match in the NIC Rx domain causes
incorrect representor steering within shared IB device ports
and must be always specified (if kernel uses this approach).
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
