25885 Commits

Author SHA1 Message Date
Lijun Ou
6dd32ded17 net/hns3: check PCI config space write
Here adds a check for the return value when calling
rte_pci_write_config.

Coverity issue: 363714
Fixes: cea37e513329 ("net/hns3: fix FLR reset")
Cc: stable@dpdk.org

Signed-off-by: Lijun Ou <oulijun@huawei.com>
2020-11-13 19:43:26 +01:00
Hongbo Zheng
d3d3132436 net/hns3: adjust code style for struct initialization
According to the rule of the used static check tool,
each member is initialized on a separate lines when
struct and union members are initialized, here is
tempting to adjust some code lines in order to remove
the warning.

Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
2020-11-13 19:43:25 +01:00
Hongbo Zheng
2427c27e03 net/hns3: use correct logging format specifiers
In current driver print log function, some print format
symbols does not match with the actual variable types.

Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
2020-11-13 19:43:25 +01:00
Ivan Malov
380f355228 net/sfc: use more robust string comparison
When it comes to comparing HW switch ID strings,
use strncmp to avoid reading past the buffer.

Fixes: e86b48aa46d4 ("net/sfc: add HW switch ID helpers")

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2020-11-13 19:43:25 +01:00
Ivan Malov
df78fe717e common/sfc_efx/base: improve MCDI version/boot clarity
Improve the clarity of the code.

Fixes: 833cfcd590e2 ("common/sfc_efx/base: add API for querying board info")
Fixes: 312191e86eb0 ("common/sfc_efx/base: refactor version / boot info get helper")

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2020-11-13 19:43:25 +01:00
Jiawen Wu
ee5cd91532 net/txgbe: remove direct use of compiler attribute
Remove direct use of compiler attribute.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-11-13 19:43:25 +01:00
Maxime Coquelin
7804bbd13a vhost: fix virtqueue initialization
This patches fixes virtqueue initialization issue causing
segfault or file descriptor being closed unexpectedly.

The wrong index was passed to init_vring_queue() by
alloc_vring_queue() when a hole in the virtqueue array was
met.

Fixes: 8acd7c213353 ("vhost: fix virtqueues metadata allocation")
Cc: stable@dpdk.org

Reported-by: Yu Jiang <yux.jiang@intel.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Tested-by: Yu Jiang <yux.jiang@intel.com>
2020-11-13 19:43:25 +01:00
Patrick Fu
45ba914134 vhost: fix async inflight packet counter
Async inflight packet counter should take failed packets into account.
Failed packets will be deducted in the error handling logic.

Fixes: 6b3c81db8bb7 ("vhost: simplify async copy completion")
Fixes: cd6760da1076 ("vhost: introduce async enqueue for split ring")
Cc: stable@dpdk.org

Signed-off-by: Patrick Fu <patrick.fu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2020-11-13 19:43:25 +01:00
Ibtisam Tariq
854dbee2ac examples/vhost_crypto: add new line character in usage
Add new line character(\n) in the usage of vhost_crypto example for
better readability

Fixes: 709521f4c2cd ("examples/vhost_crypto: support multi-core")
Cc: stable@dpdk.org

Signed-off-by: Ibtisam Tariq <ibtisam.tariq@emumba.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2020-11-13 19:43:25 +01:00
Viacheslav Ovsiienko
27b095072b net/mlx5: fix Tx queue completion on stop
The Tx queue completion production index was not reset
on Tx queue stop and there were completions remaining
from the previous queue run. This caused the wrong
completion queue operating and overall Tx queue malfunction
on queue restart.

Fixes: 161d103b231c ("net/mlx5: add queue start and stop")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 19:43:25 +01:00
Viacheslav Ovsiienko
70d83ebbbb net/mlx5: fix Rx queue completion index consistency
The Rx queue completion consumer index got temporary
wrong value pointing to the midst of the compressed CQE
session. If application crashed at the moment the next
queue restart caused handling wrong CQEs pointed by index
and losing consuming index synchronization, that made
reliable queue restart impossible.

Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error handling")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 19:43:25 +01:00
Suanming Mou
3770feb827 net/mlx5: fix hash list entry assert
The entry variable assert in the mlx5_hlist_register() function is not
correct. Remove the invalid entry variable.

Fixes: e69a59227db0 ("net/mlx5: support concurrent access for hash list")

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 19:43:25 +01:00
Dekel Peled
58df16e08c net/mlx5: fix use of local array for global error
Recent patch uses a local string array as input for function
rte_flow_error_set().
This stack memory may be later used by other code sections,
overwriting the desired error string.

This patch implements an error string for the specific case
requested, of ICMP item not supported in Verbs flow engine.

Fixes: d51475d1bfa5 ("net/mlx5: support item type error message in flow Verbs")

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 19:43:25 +01:00
Jiawei Wang
9ade91dfe8 net/mlx5: fix group value of sample suffix flow
mlx5 PMD split the sampling flow into prefix flow and suffix
flow. On the sample action translation function, the scaled
group value of suffix flow be attached into sample object and
saved into sample resource.

mlx5 PMD fetched the group value from the sample resource to
create the suffix flow. On the mlx5_flow_group_to_table
function the group value of suffix flow was scaled with table
factor again and translated into HW table. That caused the
incorrect group value of sample suffix flow.

The fix introduces a 'skip_scale' flag and sets it to 1 for the
sample suffix flow creation. On the mlx5_flow_group_to_table
function skips the scale with table factor to use the correct
group value.

Fixes: 4ec6360de37d ("net/mlx5: implement tunnel offload")

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 19:43:25 +01:00
Dong Zhou
cdbdcd46a2 net/mlx5: fix switch port id when representor in bonding
In the bonding configurations the port switch id for representors was
composed of pf index in bonding as the 1 MSB and the representor's index
as the remaining 15 LSBs. The special corner case for the host PF
representor on BF setups with representor id 0xFFFF was missed as well.

The new switch port id consists of 4 MSBs for the pf bonding index and
the remaining 12 LSBs for the representor index. The switch port id
ranges for each type of representors are as follows:

Uplink representor(AKA master): 0xFFFF
Host PF representor: 0x<pf_bond>FFF
VF representor: 0x<pf_bond>[0-FFE]

Fixes: bee57a0a3565 ("net/mlx5: update switch port id in bonding configuration")
Cc: stable@dpdk.org

Signed-off-by: Dong Zhou <dongzhou@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 19:42:40 +01:00
Dekel Peled
105d214965 net/mlx5: fix aging queue doorbell ringing
Recent patch introduced a new SQ for ASO flow hit management.
This SQ uses two WQEBB's for each WQE.
The SQ producer index is 16 bits wide.

The enqueue loop posts new WQEs to the ASO SQ, using WQE index for
the SQ management.
This 16 bits index multiplied by 2 was wrongly used also for SQ
doorbell ringing.
The multiplication caused the SW index overlapping to be out of sync
with the hardware index, causing it to get stuck.

This patch separates the WQE index management from the doorbell index
management.
So, for each WQE index incrementation by 1, the doorbell index is
incremented by 2.

Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 16:26:54 +01:00
Bing Zhao
ebda282cbb net/mlx5: fix eCPRI common header endianness
The input header of a RTE flow item is with network byte order. In
the host with little endian, the bit field order are the same as the
byte order.
When checking the eCPRI message type, the wrong field will be selected.
Fixing to use correct field.

Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 16:26:54 +01:00
Wei Huang
e6dc14c800 raw/ifpga/base: check adapter pointer before dereference
In opae_adapter_destroy(), pointer "adapter" is not validated before
passing it to opae_adapter_shm_free() and opae_adapter_mutex_close()
which dereference it.

Coverity issue: 363752
Fixes: e41856b515ce ("raw/ifpga/base: enhance driver reliability in multi-process")

Signed-off-by: Wei Huang <wei.huang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
2020-11-13 16:26:54 +01:00
Wei Huang
2414339cee raw/ifpga/base: unlock mutex on Nios init failure
In fme_nios_spi_init(), a mutex is locked for protecting nios
initialization process, the mutex is only unlocked when process
is successful, it should also be unlocked when process fail.

Coverity issue: 363751
Fixes: e41856b515ce ("raw/ifpga/base: enhance driver reliability in multi-process")

Signed-off-by: Wei Huang <wei.huang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
2020-11-13 16:26:54 +01:00
Ivan Malov
e9d5c5fb68 common/sfc_efx/base: avoid reading past buffer
Existing field ID validity check does not validate the field
descriptor availability. Make it more rigorous to avoid
reading past the buffer containing field descriptors.

Coverity issue: 363742
Fixes: 370ed675a952 ("common/sfc_efx/base: support setting PPORT in match spec")

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2020-11-13 16:26:54 +01:00
Olivier Matz
f1b9107465 net/ring: fix typo in log message
Add a missing space.

Fixes: 869bf6d222bb ("net/ring: fix coding style")
Cc: stable@dpdk.org

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-11-13 16:26:54 +01:00
Jiawen Wu
f2f55ea457 net/txgbe: replace forbidden functions
Remove rte_panic(), and use rte_atomic_thread_fence()
instead of rte_smp_[r/w]mb.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-11-13 16:26:54 +01:00
Matan Azrad
876b5d52a3 net/mlx5: fix Tx queue stop state
The Tx queue stop API doesn't call the PMD callback when the state of
the queue is stopped.
The drivers should update the state to be stopped when the queue stop
callback is done successfully or when the port is stopped.
The drivers should update the state to be started when the queue start
callback is done successfully or when the port is started.

The driver wrongly didn't update the state as started when the port
start callback was done which kept the state as stopped.
Following call to a queue stop API was not completed by ethdev layer
because the state is already stopped.

Move the state update from the Tx queue setup to the port start
callback.

Fixes: 161d103b231c ("net/mlx5: add queue start and stop")
Cc: stable@dpdk.org

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 16:26:54 +01:00
Matan Azrad
95940894f3 net/mlx5: fix Tx queue reference count check
The Txq refcnt 1 value means that there is no real reference to the
queue and only the control configurations are saved in the struct.

The patch below wrongly didn't consider it and caused a leak in the Txq
object resource.

Revert the specific update in the refcnt.

Fixes: b5c8b3e70cdf ("net/mlx5: use C11 atomics for RxQ/TxQ refcounts")

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 16:26:54 +01:00
Jiawei Wang
992e6df3da common/mlx5: free MR resource on device DMA unmap
mlx5 PMD created the MR (Memory Region) resource on the
mlx5_dma_map call to make the memory available for DMA
operations. On the mlx5_dma_unmap call the MR resource
was not freed but inserted to MR Free list for further
garbage collection.
Actual MR resource destroying happened on device stop
call. That caused the runtime out of memory in case of
application performed multiple DMA map/unmap calls.

The fix immediately frees the MR resource on mlx5_dma_unmap
call not engaging the list. The export for mlx5_mr_free
function from common PMD part is added as well.

Fixes: 989e999d9305 ("net/mlx5: support PCI device DMA map and unmap")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2020-11-13 16:26:54 +01:00
Tal Shnaiderman
8178d9be73 net/mlx5: fix SQ resources release in error flow
Fix in error flow in which the function
mlx5_txq_release_devx_sq_resources is called twice by setting the
release object to NULL after the first call

The incorrect flow was introduced in the work done on generic
object creation.

Once an error flow inside mlx5_txq_create_devx_sq_resources
occurs the function will call mlx5_txq_release_devx_sq_resources
however the released pointers are not set to NULL after the release
calls and undefined memory is released in the same call in
mlx5_txq_release_devx_resources.

This results in calls to MLX5_FREE with
an already released memory addresses and assert in mlx5_release_dbr:

EAL: Error: Invalid memory
EAL: Error: Invalid memory

PANIC in mlx5_txq_release_devx_sq_resources():
assert "(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,
 mlx5_os_get_umem_id (txq_obj->sq_dbrec_page->umem),
 txq_obj->sq_dbrec_offset)) == 0" failed

The fix is setting the released pointers to NULL after the first release
calls.

Fixes: 86d259cec852 ("net/mlx5: separate Tx queue object creations")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 16:26:54 +01:00
Ophir Munk
6c3dc9ebaa net/mlx5: fix Rx queue object allocation with MPRQ
The space for extra buffer pointers used by MPRQ routines was not
allocated in Rx queue object creation structure causing memory
corruption.
The fix allocates the extra memory for the pointers in case MPRQ is
engaged.

Fixes: a0a45e8af723 ("net/mlx5: configure Rx queue for buffer split")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-13 16:26:53 +01:00
Stephen Hemminger
1ef8c6290c net/bnxt: remove useless prefetches
Prefetching only helps performance if it is done several 100
instructions before the actual use. The purpose of the prefetch
is to read ahead, it doesn't help if the next instruction
will block.

The code in the bnxt driver was doing these unnecessary prefetches.

Fixes: 2eb53b134aae ("net/bnxt: add initial Rx code")
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Lance Richardson <lance.richardson@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2020-11-13 16:26:53 +01:00
Maxime Coquelin
048a2aa3f3 config: enable packet prefetching with Meson
With Make build system, RTE_PMD_PACKET_PREFETCH was enabled
by default. It got lost when transitioning to Meson build
system.

In order to avoid performance changes, this patch enables
packet prefetching in rte_config.h.

Fixes: 9314afb68a53 ("drivers: add infrastructure for meson build")
Cc: stable@dpdk.org

Reported-by: Marvin Liu <yong.liu@intel.com>
Suggested-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2020-11-14 10:56:30 +01:00
Yi Yang
b605df71be gro: fix packet type detection with IPv6 tunnel
For VxLAN packets, GRO will mistakenly reassemble them
if inner L3 is IPv6, inner L4 is TCP or UDP, and outer L3
is IPv4 because the value of IS_IPV4_VXLAN_TCP4/UDP4_PKT
is true for them.

This fix makes sure IS_IPV4_TCP_PKT, IS_IPV4_UDP_PKT,
IS_IPV4_VXLAN_TCP4_PKT and IS_IPV4_VXLAN_UDP4_PKT can make
decision precisely.

Fixes: e2d811063673 ("gro: support VXLAN UDP/IPv4")
Fixes: 1ca5e6740852 ("gro: support UDP/IPv4")
Fixes: 9e0b9d2ec0f4 ("gro: support VxLAN GRO")
Fixes: 0d2cbe59b719 ("lib/gro: support TCP/IPv4")
Cc: stable@dpdk.org

Signed-off-by: Yi Yang <yangyi01@inspur.com>
Acked-by: Jiayu Hu <jiayu.hu@intel.com>
2020-11-14 10:56:30 +01:00
Viacheslav Ovsiienko
eb63ec0e56 net/mlx5: fix UAR used by ASO queues
The dedicated UAR was allocated for the ASO queues.
The shared UAR created for Tx queues can be used instead.

Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-14 10:56:30 +01:00
Viacheslav Ovsiienko
b9aa4ba7ce vdpa/mlx5: fix UAR allocation
This patch provides the UAR allocation workaround for the
hosts where UAR allocation with Write-Combining memory
mapping type fails.

Fixes: 8395927cdfaf ("vdpa/mlx5: prepare HW queues")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-14 10:56:30 +01:00
Viacheslav Ovsiienko
e8f05161eb regex/mlx5: fix UAR allocation
This patch provides the UAR allocation workaround for the
hosts where UAR allocation with Write-Combining memory
mapping type fails.

Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-14 10:56:30 +01:00
Viacheslav Ovsiienko
9cc0e99c81 common/mlx5: share UAR allocation routine
This patch introduces the routine to allocate the UAR (User
Access Region) with various memory mapping types. The origin
patch being fixed provided the UAR allocation workaround
for the mlx5 net PMD only. As it was found the other mlx5
based drivers - vdpa and regex are affected by the issue
as well and must be fixed.

Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2020-11-14 10:56:30 +01:00
Ciara Power
b0dcd61052 usertools: fix CPU layout script to be PEP8 compliant
The pycodestyle tool flagged the following issues, which are now fixed.

$ pycodestyle cpu_layout.py
  cpu_layout.py:18:5: E722 do not use bare 'except'
  cpu_layout.py:62:14: E231 missing whitespace after ','

Fixes: deb87e6777c0 ("usertools: use sysfs for CPU layout")
Fixes: c9208f1dc967 ("usertools: fix CPU layout with python 3")
Cc: stable@dpdk.org

Signed-off-by: Ciara Power <ciara.power@intel.com>
2020-11-13 15:40:21 +01:00
Bruce Richardson
242623459e raw/ioat: fix queue index calculation
Coverity flags a possible problem where the 8-bit wq_idx value may have
errors when shifted and sign-extended to pointer size. Since this can
only occur if the shift index is larger than any expected value from
hardware, it's unlikely to cause any real problems, but we can eliminate
any possible errors, and the coverity issue, by explicitly typecasting
the uint8_t value to uintptr_t before any shift operations occur.

Coverity issue: 363695
Fixes: a33969462135 ("raw/ioat: fix work-queue config size")

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2020-11-13 15:30:08 +01:00
Nick Connolly
52a7cb0ad0 build: fix MS linker flag with meson 0.54
Meson versions >= 0.54.0 include support for handling /implib
with msvc link. Specifying it explicitly causes failures when
linking against the dll. Tested using Link 14.27.29112.0 and
Clang 11.0.0.

There were a number of changes to the way that import libraries
are handled between 0.47.1 and 0.54.0. Only make the change
for >= 0.54.0, leaving the behaviour unchanged for earlier
versions.

Fixes: 77cca7ccec13 ("build: fix drivers library path on Windows")
Cc: stable@dpdk.org

Signed-off-by: Nick Connolly <nick.connolly@mayadata.io>
Tested-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Khoa To <khot@microsoft.com>
2020-11-13 15:13:16 +01:00
Nick Connolly
5c7d869487 build: fix install on Windows
Don't run symlink-drivers-solibs.sh as part of 'install' because
Windows doesn't support shell scripts.

Fixes: 82ba4416dd87 ("build: add module definition files for Windows")
Cc: stable@dpdk.org

Signed-off-by: Nick Connolly <nick.connolly@mayadata.io>
Tested-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Ranjit Menon <ranjit.menon@intel.com>
2020-11-13 15:13:10 +01:00
Ibtisam Tariq
fc48d8a5b2 examples/qos_sched: fix usage string
The short option written for interactive mode is --i in usage of
this qos_sched example. Actually, it is -i.

Fixes: cfd5c971e5e ("examples/qos_sched: add stats")
Cc: stable@dpdk.org

Signed-off-by: Ibtisam Tariq <ibtisam.tariq@emumba.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
2020-11-13 14:25:57 +01:00
Cristian Dumitrescu
5725870c8c table: fix exact match SWX table lookup
Fix for the exact match lookup function.

Fixes: d0a00966618b ("table: add exact match SWX table")

Signed-off-by: Churchill Khangar <churchill.khangar@intel.com>
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
2020-11-13 13:55:07 +01:00
Cristian Dumitrescu
5adff62e5f doc: describe the SWX pipeline type
Add the new SWX pipeline type to the Programmer's Guide.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
2020-11-13 13:55:07 +01:00
Dharmik Thakkar
40892ddb39 crypto/armv8: replace meson option with pkg-config support
With pkg-config support available within AArch64crypto library,
meson option 'armv8_crypto_dir' can be removed.
PKG_CONFIG_PATH environment variable should be set appropriately
to use the crypto library.

Suggested-by: Thomas Monjalon <thomas@monjalon.net>
Signed-off-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
2020-11-13 10:34:04 +01:00
Ruifeng Wang
8fce34cd0a eal/arm: fix clang build of native target
When doing Clang build with '-mcpu=native' on N1 platform, build failed
with:
../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
	error: instruction requires: lse
__ATOMIC128_CAS_OP(__cas_128_release, "caspl")

This is because native detection for Neoverse N1 was added in Clang-11.
Prior version of Clang's assembler doesn't know LSE support on hardware.
Fixed this for Clang earlier than version 11 by specifying architecture
for assembler.
Referred to [1] for this fix.

Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
Cc: stable@dpdk.org

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0d5896bd356cd577f9710a02d7a474cdf58426b

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-11-13 10:30:48 +01:00
David Christensen
2d0a972cd6 vfio: use static window sizing for sPAPR IOMMU
The SPAPR IOMMU requires that a DMA window size be defined before memory
can be mapped for DMA. Current code dynamically modifies the DMA window
size in response to every new memory allocation which is potentially
dangerous because all existing mappings need to be unmapped/remapped in
order to resize the DMA window, leaving hardware holding IOVA addresses
that are temporarily unmapped.  The new SPAPR code statically assigns
the DMA window size on first use, using the largest physical memory
memory address when IOVA=PA and the highest existing memseg virtual
address when IOVA=VA.

Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
2020-11-13 09:35:18 +01:00
David Marchand
cb2587644e devtools: fix directory filter in forbidden token check
checkpatches.sh current complains on a patch [1] adding
ALLOW_EXPERIMENTAL_API in an example while this check is for app, lib
and drivers directories:

Warning in examples/ethtool/ethtool-app/Makefile:
Using experimental build flag for in-tree compilation

The regexp on entering files concerned by this filter is incorrect.
In the [1] case, the file full name is matched against "app" rather than
"+++ b/app".

1: https://patchwork.dpdk.org/patch/83902/

Fixes: 7413e7f2aeb3 ("devtools: alert on new calls to exit from libs")
Cc: stable@dpdk.org

Signed-off-by: David Marchand <david.marchand@redhat.com>
2020-11-13 09:35:04 +01:00
Bruce Richardson
3495a68f2a examples: stop processing meson file if build impossible
Once it has been determined that an example cannot be built, there is
little point in continuing to process the meson.build file for that
example, so we can use subdir_done() to return to the calling file.
This can potentially prevent problems where later statement in the file
may cause an error on systems where the app cannot be built, e.g. on
Windows or FreeBSD.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2020-11-12 19:33:36 +01:00
Bruce Richardson
b334236abd examples/l2fwd-keepalive: skip meson build if no librt
When librt is not present on a system, processing the meson.build file
for this example application causes an error. Make the library
non-mandatory and just mark the example as unbuildable if it is
not present.

Fixes: 89f0711f9ddf ("examples: build some samples with meson")
Cc: stable@dpdk.org

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2020-11-12 19:33:10 +01:00
Bruce Richardson
e5b95003f1 examples: fix flattening directory layout on install
By installing the examples one-by-one in a loop in the examples
meson.build file we effectively flattened out the structure of the examples
folder and omitted some common and shared subfolders that were never
directly built.  Instead, we can remove the loop and just have the whole
"examples" folder installed as-is in a single statement, preserving its
directory structure, and thereby fixing the build of a number of the
examples.

Fixes: 2daf565f91b5 ("examples: install as part of ninja install")
Cc: stable@dpdk.org

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2020-11-12 19:33:06 +01:00
Thomas Monjalon
4630290af4 mbuf: move pool pointer in first half
According to the Technical Board decision
(http://mails.dpdk.org/archives/dev/2020-November/191859.html),
the mempool pointer in the mbuf struct is moved
from the second to the first half.
It may increase performance in some cases
on systems having 64-byte cache line, i.e. mbuf split in two cache lines.

Due to this change, all fields after "pool" are moved up.
Hopefully no vector data path is impacted.

Moving this field gives more space to dynfield1
while dropping the temporary dynfield0.

This is how the mbuf layout looks like (pahole-style):

word  type                              name                byte  size
 0    void *                            buf_addr;         /*   0 +  8 */
 1    rte_iova_t                        buf_iova          /*   8 +  8 */
      /* --- RTE_MARKER64               rearm_data;                   */
 2    uint16_t                          data_off;         /*  16 +  2 */
      uint16_t                          refcnt;           /*  18 +  2 */
      uint16_t                          nb_segs;          /*  20 +  2 */
      uint16_t                          port;             /*  22 +  2 */
 3    uint64_t                          ol_flags;         /*  24 +  8 */
      /* --- RTE_MARKER                 rx_descriptor_fields1;        */
 4    uint32_t             union        packet_type;      /*  32 +  4 */
      uint32_t                          pkt_len;          /*  36 +  4 */
 5    uint16_t                          data_len;         /*  40 +  2 */
      uint16_t                          vlan_tci;         /*  42 +  2 */
 5.5  uint64_t             union        hash;             /*  44 +  8 */
 6.5  uint16_t                          vlan_tci_outer;   /*  52 +  2 */
      uint16_t                          buf_len;          /*  54 +  2 */
 7    struct rte_mempool *              pool;             /*  56 +  8 */
      /* --- RTE_MARKER                 cacheline1;                   */
 8    struct rte_mbuf *                 next;             /*  64 +  8 */
 9    uint64_t             union        tx_offload;       /*  72 +  8 */
10    struct rte_mbuf_ext_shared_info * shinfo;           /*  80 +  8 */
11    uint16_t                          priv_size;        /*  88 +  2 */
      uint16_t                          timesync;         /*  90 +  2 */
11.5  uint32_t                          dynfield1[9];     /*  92 + 36 */
16    /* --- END                                             128      */

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
2020-11-12 16:39:10 +01:00
Thomas Monjalon
43314d97e2 drivers: disable OCTEON TX2 in 32-bit build
The drivers for OCTEON TX2 are not supported in 32-bit mode.

Suggested-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-11-12 16:39:10 +01:00