The -march=atom flag is for older atom CPUs and don't support SSE4 which
is the minimum requirement for DPDK. And in fact, the current atom CPUs
support SSE4. So this patch removes atom as a target for DPDK builds and
adds a silvermont replacement instead.
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
NXP Copyright has been wrongly worded with '(c)' at various places.
This patch removes these extra characters. It also removes
"All rights reserved".
Only NXP copyright syntax is changed. Freescale copyright is not
modified.
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
Replace the incorrect reference to "Cavium Networks", "Cavium Ltd"
company name with correct the "Cavium, Inc" company name in
copyright headers.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
armv8-a has optional CRYPTO extension which adds the
AES, PMULL, SHA1 and SHA2 capabilities. -march=armv8-a+crypto
enables code generation for the ARMv8-A architecture together
with the optional CRYPTO extensions.
Added the following flags to detect the corresponding
capability at compile time.
* RTE_MACHINE_CPUFLAG_AES
* RTE_MACHINE_CPUFLAG_PMULL
* RTE_MACHINE_CPUFLAG_SHA1
* RTE_MACHINE_CPUFLAG_SHA2
At run-time, the following flags can be used to detect the
capabilities.
* RTE_CPUFLAG_AES
* RTE_CPUFLAG_PMULL
* RTE_CPUFLAG_SHA1
* RTE_CPUFLAG_SHA2
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
Reviewed-by: Jan Viktorin <viktorin@rehivetech.com>
Increase the default baseline from "core2" architecture to "corei7". This
means that all builds will have SSE4.2 support included, and we can remove
special case manipulation of CFLAGS for the same. Naturally, this does mean
that some machines that previously could run DPDK now can't do so, but
hardware with SSE4.2 has been around for almost a decade now, so this
should not be a major problem.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Fixing typos across dpdk source code using codespell utility.
Skipped the ethdev driver's base code fixes to keep the base
code intact.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
DPAA2 devices now support cortex-a72. They no longer support a57.
Also fp and simd is no more required to be stated explicitly for
standard a72 core.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The environment variable CROSS must be set when using a cross-toolchain.
However it is counter intuitive to set a default value, considering
the toolchain required to build this architecture is well known.
It is especially weird when using a native toolchain and requiring to
unset this variable on the command line.
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Reviewed-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This patch introduces dpaa2 machine target to address difference
in cpu parameter, number of core to 8 and no numa support
w.r.t default armv8-a machine
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The dpdk build system passes -mfloat-abi=softfp, which makes the build fail
when the selected ABI is EABIhf. The dpdk build system should not make
assumptions on the selected ARM ABI.
Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
ARMv7 machines have usually the NEON available.
Customization of the -mfpu=neon must be done by hand or by defining
another machine rte.vars.mk.
So, the CONFIG_RTE_ARCH_ARM_NEON is useless (and confusing).
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
The CONFIG_RTE_MACHINE must not contain hyphens to work correctly. This was
initially done only for the file name defconfig_arm-armv7a-linuxapp-gcc. This
patch fixes install-sdk goal. Otherwise, it creates a wrong directory for this
platform.
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
by default, all the targets will be configured with the 64-byte cache line
size, targets which have different cache line size can be overridden
through target specific config file.
Selected ThunderX and power8 as CONFIG_RTE_CACHE_LINE_SIZE=128 targets
based on existing configuration.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
created the new xgene1 machine target to address the difference
in optional armv8-a CRC extension availability compared to
default armv8-a machine target(enabled CRC extension by default)
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
armv8-a has optional CRC32 extension, march=armv8-a+crc enables code
generation for the ARMv8-A architecture together with
the optional CRC32 extensions.
added RTE_MACHINE_CPUFLAG_CRC32 to detect the availability of
CRC32 extension in compile time. At run-time, The RTE_CPUFLAG_CRC32
can be used to find the availability.
armv8-a+crc target support added in GCC 4.9,
Used inline assembly and emulated __ARM_FEATURE_CRC32 to work
with tool-chain < 4.9
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Created the new thunderx machine target to address difference
in "cache line size" and "-mcpu=thunderx" vs default armv8-a machine target
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Make DPDK run on ARMv7-A architecture. This patch assumes
ARM Cortex-A9. However, it is known to be working on Cortex-A7
and Cortex-A15.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Acked-by: David Marchand <david.marchand@6wind.com>
This commit adds support for the TILE-Gx platform, as well as the TILE
CPU architecture. This architecture port is fairly simple due to its
reliance on generics for most arch stuff.
Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>
Signed-off-by: Zhigang Lu <zlu@ezchip.com>
To make DPDK run on IBM Power architecture, configuration files for
Power architecuture are added. Also, the compiling related .mk files are
added.
Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Acked-by: David Marchand <david.marchand@6wind.com>
Add a special case to the native target makefile, where we check if
-march=native shows SSE4.2 support. If it does not, then not everything may
build, so we check if the hardware supports SSE4.2, and use a corei7 target
explicitly to get the SSE4.2 support.
Then ACL library, which requires SSE4.2, can be re-enabled for FreeBSD.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Zhaochen Zhan <zhaochen.zhan@intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
This commit removes trailing whitespace from lines in files. Almost all
files are affected, as the BSD license copyright header had trailing
whitespace on 4 lines in it [hence the number of files reporting 8 lines
changed in the diffstat].
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
[Thomas: remove spaces before tabs in libs]
[Thomas: remove more trailing spaces in non-C files]
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Add support for haswell based systems.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: David Marchand <david.marchand@6wind.com>
For cases where the compilation microarchitecture is explicitly given, we
extract the cpu-flags to use from the compiler rather than hard-coding. This
means that we will only ever use instruction sets supported by the compiler,
rather than having a case where the uarch and the Intel DPDK both support a
given instruction-set, but the compiler does not.
In the case where 'native' uarch support is requested, the same mechanism is
also used to detect the instruction-sets supported
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: David Marchand <david.marchand@6wind.com>
