TC nodes CIR configuration is not supported. In order to configure PIR,
the corresponding adminq command should not include the flag for CIR.
Since the TC node info has this flag by default, it is supposed to delete
this flag for TC nodes before sending the adminq command.
Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Move replay_pre_init function to interface.
Add further MAC rules, despite unicast address is already on list.
Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Add ice_aqc_sw_gpio struct to ice_aq_desc
This change allows us to do SW_GPIO AQ cmd transactions
over ice_aq_send_cmd() interface.
Signed-off-by: Siddaraju DH <siddaraju.dh@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Add function ice_is_e810t() to be able to distinguish if hardware is
E810T based or not.
Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
After starting the timestamping block, hardware begins calculating
precise offsets through a process of vernier calibration. This process
measures the effective phase offset of the various internal clocks used
in the PHY.
Once hardware completes these measurements, the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers are updated to indicate that the hardware
offset measurements are done.
This process does not happen immediately, but requires that at least one
packet be sent or received in order for the offset in that direction to
be calculated.
This poses a problem in some setups, because software expects the first
packet sent to be timestamped. This most often occurs if the clock time
is set by an application during startup. This set time command triggers
a PHY restart. Because of this, the timestamping block is reset, and
timestamps are not enabled until vernier calibration is complete. Since
this process won't complete until at least one packet is sent through
the PHY, timestamps of the very first packet sent will not be obtained.
This can result in the application failing due to missing timestamps.
To avoid this, allow starting the PHY in bypass mode. This mode enables
timestamps immediately, and skips adding the precise offset measurement.
This reduces the accuracy of the timestamp slightly, but ensures that we
get a reasonable value for the first packet.
The driver can continue monitoring the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers and exit bypass mode once the total
calibration is completed. In this way, once calibration is complete, the
timestamps will have the precise offset, but we do not break
applications which expect to be able to timestamp immediately.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Rework the comment around checking PFC mode to make it clear why we are
checking the mode after sending the command.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Move the implementation of Vernier calibration from Linux core ice_ptp.c
into the shared ice_ptp_hw.c file.
This implementation was recently refactored in Linux, so the move should
be verbatim with the latest Linux code that we had implemented.
This includes a new constant table with pre-determined values based on
link speed, new functions to aide in reading the multi-register values
from the PHY, functions to program the PAR/PCS conversion ratios, and
the UIX conversion ratios, functions to program the total Tx and Rx
offset after vernier calibration in the hardware completes, and finally
a function to start and stop the PHY timestamping block.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
The E822 device clock might come from a variety of different sources,
called TIME_REFs. The firmware reports the current TIME_REF as part of
its function capabilities, which the driver caches when it loads.
Add an accessor function to look up the current TIME_REF from the
capabilities. This reduces line length significantly and also avoids
a tight coupling to the capabilities structure.
In some cases, TIME_REF might change at run time. This can occur in the
event that the CGU registers are updated. When this happens, its
possible that the capabilities structure can be out of date until the
capabilities are re-read.
Add a setter function to update the TIME_REF when this occurs. The
driver can call this function after updating the CGU to ensure that the
TIME_REF in the capabilities structure is up to date, without needing to
re-read the entire capabilities from firmware.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Before the device PTP hardware clock can be initialized, some steps must
be taken by the driver. This includes writing some registers and
initializing the PHY.
Some of these steps are distinct depending on the device type (E810 or
E822). Additionally, a future change will introduce more steps for E822
devices to program the Clock Generation Unit.
Introduce ice_ptp_init_phc as well as device-specific sub-functions for
e810 and e822 devices.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Adding macros for shift and masking of the lower timestamp work in the
Rx flex descriptor. The LSB of the timestamp-low word indicates the
validity of the timestamp while the rest 7 bits contain the timestamp.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Ethertype was traded as VLAN tpid in dummy packets with VLAN.
This led to a problem when user wanted to add filter for VLAN and
ethertype.
Change ice_vlan_hdr to reflect correct order of VLAN fields in
packets (VLAN tpid, VLAN id). Correct all dummy packets with VLAN.
Move VLAN fields before ethertype and change offsets. Leave values
from dummy packets unchanged as they fit to new VLAN layout.
Order of offsets in ice_prot_ext_tbl_entry for VLAN protocol should
reflect order of fields in ice_vlan_hdr. However, hardware doesn't
support matching on all tpid. This should be done by matching on
packet flags. There is no FV word with protocol for VLAN and offset
2. Because of that, adding vlan tpid with not zero mask will lead
to error in creating recipe.
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
In order to support switch rule for ethertype filter
with ipv6 ethertype id, it has to check ethertype and
then find a proper dummy packet. There was a silent
assumption that packet is ipv4, unless src or dst ipv6
address is specified in a flow.
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
The ice hardware supports exposing a hardware clock for high precision
timestamping. This is primarily intended for accelerating the Precision
Time Protocol.
Add several low level functions intended to be used as the basis for
enabling the device clock, and ensuring that the port timers are
synchronized properly.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Build on aarch64 with clang-10 has warning:
i40e_rxtx.c:3228:1:
warning: unused function 'get_avx_supported' [-Wunused-function]
The function is used in x86 specific path. Moved it into ifdef
to fix build on non-x86.
Fixes: c30751afc360 ("net/i40e: fix data path selection in secondary process")
Cc: stable@dpdk.org
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This patch fixes the reversed priority of DCF switch rule. Priority 0
and 1 are supported, and priority 0 should be the highest priority.
Fixes: 2321e34c23b3 ("net/ice: support flow priority for DCF switch filter")
Cc: stable@dpdk.org
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
For N1 platform, packet mbuf load and descs load are hot spots to limit
the performance for "desc_to_ptype_v" and "desc_to_olflags_v" functions
in i40e rx NEON path. This is because packet mbuf and descs are evicted
from l1d-cache to l2d-cache.
To reduce l1d-cache-misses and improve the performance, change the code
order and move "desc_to_ptype_v" and "desc_to_olflags_v" functions
forward to the location, where packet mbuf and descs are just loaded.
Test Result:
dpdk:21.08-rc1
gcc-9
For n1sdp, the patch improves the performance by 1.8%.
For thunderx2, no performance changes.
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Rearrange the code in logical order for better readability and
maintenance convenience in Rx NEON path.
No performance change with this patch in arm platform.
Suggested-by: Joyce Kong <joyce.kong@arm.com>
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
For the loop to process packets in Rx vector path, some notes for the
code are wrong, fix these errors.
Fixes: 7092be8437bd ("fm10k: add vector Rx")
Fixes: c3def6a8724c ("net/i40e: implement vector PMD for altivec")
Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM")
Fixes: 9ed94e5bb04e ("i40e: add vector Rx")
Fixes: 319c421f3890 ("net/avf: enable SSE Rx Tx")
Fixes: 1162f5a0ef31 ("net/iavf: support flexible Rx descriptor in SSE path")
Fixes: c68a52b8b38c ("net/ice: support vector SSE in Rx")
Fixes: cf4b4708a88a ("ixgbe: improve slow-path perf with vector scattered Rx")
Cc: stable@dpdk.org
Suggested-by: Ruifeng Wang <ruifeng.wang@arm.com>
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Since meson 0.59.0 version, the extract_all_objects() API
need to pass explicit boolean value.
To remove the following warning[1], added explicit `true` for
extract_all_objects() use in codebase whever there is
no argument.
[1]
WARNING: extract_all_objects called without setting recursive
keyword argument. Meson currently defaults to
non-recursive to maintain backward compatibility but
the default will be changed in the future.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Start a new release cycle with empty release notes.
The ABI version becomes 22.0.
The map files are updated to the new ABI major number (22).
The ABI exceptions are dropped and CI ABI checks are disabled because
compatibility is not preserved.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: David Marchand <david.marchand@redhat.com>
mlx5_dev_check_sibling_config() API was updated to allow newly
spawned port locate existing sibling devices.
PMD port initialization for Windows OS was not updated
for the new API prototype:
drivers/net/mlx5/windows/mlx5_os.c:457:50: error:
too few arguments to function call, expected 3, have 2
err = mlx5_dev_check_sibling_config(priv, config);
The patch fixes mlx5_dev_check_sibling_config call for Windows OS.
Fixes: e9d420dfc2d0 ("net/mlx5: fix find sibling devices")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
PCI, vmbus, and auxiliary drivers printed a warning
when NUMA node had been reported as (-1) or not reported by OS:
EAL: Invalid NUMA socket, default to 0
This message and its level might confuse users because the configuration
is valid and nothing happens that requires attention or intervention.
It was also printed without the device identification and with an indent
(PCI only), which is confusing unless DEBUG logging is on to print
the header message with the device name.
Reduce level to INFO, reword the message, and suppress it when there is
only one NUMA node because NUMA awareness does not matter in this case.
Also, remove the indent for PCI.
Fixes: f0e0e86aa35d ("pci: move NUMA node check from scan to probe")
Fixes: 831dba47bd36 ("bus/vmbus: add Hyper-V virtual bus support")
Fixes: 1afce3086cf4 ("bus/auxiliary: introduce auxiliary bus")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
The routine mlx5_eth_find_next() and related iterating macro
MLX5_ETH_FOREACH_DEV is used to iterate through sibling devices (all
representors share the same configuration and switching domain) on top
of specified root device.
The root device parameter was specified as NULL, and it caused
missing siblings in iteration during representor device probing,
causing:
1. allocating new domain_id for the device being probed.
2. discrepancy in representor configurations and potential overall
driver malfunctions.
Fixes: 56bb3c84e982 ("net/mlx5: reduce PCI dependency")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Meters in one hierarchy might support different domains. For
example, one meter may support ingress only, but the root meter
can support all the domains.
If the later meter in the meter hierarchy wrongly doesn't inherit
the first meter's domains, it will lead to invalid domain table
access.
Fix is when creating meter hierarchy, try to inherit the first meter
domains in the meter hierarchy.
Fixes: a3b7af90baba ("net/mlx5: validate meter action in policy")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
When a flow rule uses a meter without any modify packet action,
there will be an internal drop flow with meter counter created,
matching the same 5-tuple as the original flow.
In this case, the meter flow count action is wrongly reused as the
original flow counter, leading to wrong flow statistics.
Add a check in the count action translation to detect the meter case
and use the meter drop dedicated counter in the meter 5-tuple flow
only.
Fixes: f3191849f2c2 ("net/mlx5: support flow count action handle")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Currently, there are two types of drop action implementation
in the PMD. One is the DR (Direct Rules) dummy placeholder drop
action and another is the dedicated dummy queue drop action.
When creates flow on the root table with DR drop action, the
action will be converted to MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP
Verbs attribute in rdma-core.
In some inbox systems, MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP Verbs
attribute may not be supported in the kernel driver. Create flow
with drop action on the root table will be failed as it is not
supported. In this case, the dummy queue drop action should be
used instead of DR dummy placeholder drop action.
This commit adds the DR drop action support detect on the root
table. If MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP Verbs is not
supported in the system, a dummy queue will be used as drop
action.
Fixes: da845ae9d7c1 ("net/mlx5: fix drop action for Direct Rules/Verbs")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
In the recent update, the misc5 matcher was introduced to
match VxLAN header extra fields. However, ConnectX-5
doesn't support misc5 for the UDP ports different from
VXLAN's standard one (4789).
Need to fall back to the previous approach and use legacy
misc matcher if non-standard UDP port is recognized
in VxLAN flow.
Fixes: 630a587bfb37 ("net/mlx5: support matching on VXLAN reserved field")
Cc: stable@dpdk.org
Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
All active ports that belong to the same E-switch share domain_id
value.
Port initialization procedure searches through a database for existing
port with matching properties. New domain_id allocated if match was
not located. Otherwise, new port inherits existing domain_id.
Port initialization did not pass enough info to search procedure to
find existing matches. Therefore, each port was created with a private
domain_id value. As the result, port_id flow action failed because it
could not match ports in a rule to E-switch.
The patch adds dpdk_dev with port properties to device search.
Fixes: 56bb3c84e982 ("net/mlx5: reduce PCI dependency")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Compression Level is interpreted by each PMD differently.
However, lower numbers give faster compression
at the expense of compression ratio, while higher numbers
may give better compression ratios but are likely slower.
The level affects the block size, which affects performance,
the bigger the block, the faster the compression is.
The problem was that higher levels caused bigger blocks:
size = min_block_size - 1 + level.
the solution is to reverse the above:
size = max_block_size + 1 - level.
Fixes: 39a2c8715f8f ("compress/mlx5: add transformation operations")
Cc: stable@dpdk.org
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
For Thor, the number of action records is being wrongly configured
to 128 because of incorrect definition of divider. This results in
an incorrect number of action records being negotiated with the FW.
Remove the divider from the templates and delete the logic which
uses the field in the resource manager logic.
Fixes: 3fe124d2536c ("net/bnxt: support Thor platform")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Tested-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
In crypto driver probing, there are two validations after context
allocation.
When one of them fails, the context structure was not freed what caused
a memory leak.
Free it.
Fixes: debb27ea3442 ("crypto/mlx5: create login object using DevX")
Fixes: e8db4413cba5 ("crypto/mlx5: add keytag configuration")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Fix return code when asymmetric crypto
or compression service is selected on GEN4 devices.
Fixes: 8f393c4ffdc1 ("common/qat: support GEN4 devices")
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
When the PMD is removed, rte_cryptodev_pmd_release_device
is called which frees cryptodev->data, and then tries to free
cryptodev->data->dev_private, which causes the heap use
after free issue.
A temporary pointer is set before the free of cryptodev->data,
which can then be used afterwards to free dev_private.
Fixes: bfe2ae495ee2 ("crypto/octeontx: add PMD skeleton")
Cc: stable@dpdk.org
Reported-by: Zhihong Peng <zhihongx.peng@intel.com>
Signed-off-by: Akhil Goyal <gakhil@marvell.com>
This patch fixes the raw data path dequeue burst fail problem.
Previously in case the queue is full and not all packets
asked to be dequeued are processed, the dequeue burst will
never happen.
Fixes: c21574edc52a ("cryptodev: add dequeue count parameter in raw API")
Cc: stable@dpdk.org
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Fix possible access of an array by negative index in function
qat_sym_qp_setup.
Coverity issue: 372131, 372134
Fixes: 8f393c4ffdc1 ("common/qat: support GEN4 devices")
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Adding changes to asymmetric ECDSA messages to align with
the new ucode for octeontx2 device.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Adding changes to asymmetric ECDSA messages to align with
the new ucode for cnxk device.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
New ucode expects const values A and B for asymmetric ECDSA
messages. Adding roc support for this.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
In a few cases with Thor device, PMD can segfault when VF
representors are specified. Temporarily fix it by preventing
VF reps for Thor device. This will be addressed in next release.
Fixes: 3fe124d2536c ("net/bnxt: support Thor platform")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
The flow counters is reduced from 8192 to 6912 for Whitney
for compatibility with different versions of FW.
The FW resource manager splits resources for flow offload
and other use cases. A higher value used for flow offload
by the PMD can cause overriding the resources set aside by
FW. This in turn can lead to FW rejecting filter creation
requests during initialization.
Use a smaller safe value to avoid these issues.
Fixes: 6fad9115101c ("net/bnxt: reorganize ULP template directory structure")
Cc: stable@dpdk.org
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Fix the resource qcap list handling to use size based on
FW response.
The size of resource qcap list could be different when FW
and application are not matching. Application should be able
to handle this scenario when the FW is older and the size of
qcap is smaller. Failure to do this causes initialization failure.
This patch is needed for backward compatibility on different
firmware versions.
Fixes: 873661aa641a1 ("net/bnxt: support shared session")
Cc: stable@dpdk.org
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reads to Tx queue FC memory need to be atomic to avoid cores using
same Tx queue spinning on stale values.
Fixes: 313e884a22fd ("event/cnxk: support Tx adapter fast path")
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
