The arch-specific directories arm, ppc and x86 in common/include/arch/
are moved as include/ sub-directories of respective arch directories:
- arm/include/
- ppc/include/
- x86/include/
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: David Marchand <david.marchand@redhat.com>
Broadcom Stingray is armv8 CPU having cortex-a72. The implementor ID is
0x41 (arm) and the primary part number is 0xd08 (cortex-a72).
Signed-off-by: Qingmin Liu <qingmin.liu@broadcom.com>
The rte_wait_until_equal_xx APIs abstract the functionality of
'polling for a memory location to become equal to a given value'.
Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled
by default. When it is enabled, the above APIs will call WFE instruction
to save CPU cycles and power.
From a VM, when calling this API on aarch64, it may trap in and out to
release vCPUs whereas cause high exit latency. Since kernel 4.18.20 an
adaptive trapping mechanism is introduced to balance the latency and
workload.
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
Meson fails to find a pkg-config executable if pkgconfig
isn't set for aarch64. The environment variable `PKG_CONFIG_PATH`
is useless in this case, and meson fails to locate dependencies
that are built in non-standard paths.
Signed-off-by: Ali Alnubani <alialnu@mellanox.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Add the make and meson based build infrastructure for the eMAG platform
from Ampere Computing corp., which is a 64-bit ARM processor with 32
Armv8 64-bit CPU cores. For more information, refer to:
https://amperecomputing.com/product/
Signed-off-by: Jerry Hao OS <jerryhao@os.amperecomputing.com>
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
To make the list complete and consistent, add cortex-a76 configuration.
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Arm N1 SDP is an infrastructure segment development platform
based on armv8.2-a Neoverse N1 CPU. For more information, refer to:
https://community.arm.com/developer/tools-software/oss-platforms/w/
docs/440/neoverse-n1-sdp
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
dpaa and dpaa2 config have evolved to be same. The same binary
can now work across the platforms. So, there is no need to maintain
two different build configs.
The dpaa config shall work for both generation of dpaa platforms.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
This patch adds the implementation of the 128-bit atomic compare
exchange API on aarch64. Using 64-bit 'ldxp/stxp' instructions
can perform this operation. Moreover, on the LSE atomic extension
accelerated platforms, it is implemented by 'casp' instructions for
better performance.
Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, this
patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable
the 'cas' version on older version compilers.
For octeontx2, we make sure that the lse (and other) extensions are
enabled even if the compiler does not know of the octeontx2 target
cpu.
Since direct x0 register used in the code and cas_op_name() and
rte_atomic128_cmp_exchange() is inline function, based on parent
function load, it may corrupt x0 register aka break aarch64 ABI.
Define CAS operations as rte_noinline functions to avoid an ABI
break [1].
1: https://git.dpdk.org/dpdk/commit/?id=5b40ec6b9662
Suggested-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Tested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Since gcc-8.3(I tried 8.3 and 9.1), the meson build failed on ThunderX2.
It got the following compiling errors:
/usr/lib/gcc/aarch64-linux-gnu/9/include/arm_neon.h:26493:1: error:
inlining failed in call to always_inline ‘vmull_p64’:
target specific option mismatch 26493 | vmull_p64 (poly64_t a, poly64_t b)
Fixes: 7286c9d723 ("config: add thunderx2 machine")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Jingzhao Ni <jingzhao.ni@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch introduces armada target to address difference
in number of cores, no numa support
Signed-off-by: Liron Himi <lironh@marvell.com>
Reviewed-by: Alan Winkowski <walan@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Gavin Hu <gavin.hu@arm.com>
Per armv8 crypto extension support, make build always enable it by default
as long as compiler supports the feature while meson build only enables it
for 'default' machine of generic armv8 architecture.
It is known that not all the armv8 platforms have the crypto extension. For
example, Mellanox BlueField has a variant which doesn't have it. If crypto
enabled binary runs on such a platform, rte_eal_init() fails.
'+crypto' flag currently implies only '+aes' and '+sha2' and enabling it
will generate the crypto instructions only when crypto intrinsics are used.
For the devices supporting 8.2 crypto or newer, compiler could generate
such instructions beyond intrinsics or asm code. For example, compiler can
generate 3-way exclusive OR instructions if sha3 is supported. However, it
has to be enabled by adding '+sha3' as of today.
In DPDK, armv8 cryptodev is the only one which requires the crypto support.
As it even uses external library of Marvell which is compiled out of DPDK
with crypto support and there's run-time check for required cpuflags,
crypto support can be disabled in DPDK.
Cc: stable@dpdk.org
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Tested-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Mellanox BlueField is armv8 CPU having cortex-a72. The implementor ID is
0x41 (arm) and the primary part number is 0xd08 (cortex-a72).
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Current default cache line size for armv8 CPUs having Implementor ID of
0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores
is changed to 16 from 256.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
When building for generic distribution we need a stable baseline
architecture, or depending on the build worker the result will vary.
Force the default flags if the user explicitly sets machine=default
at configuration time.
Fixes: b1d48c4118 ("build: support ARM with meson")
Cc: stable@dpdk.org
Signed-off-by: Luca Boccassi <bluca@debian.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Remove the following warning by comparing string to string.
config/arm/meson.build:153: WARNING: Trying to compare values of
different types (list, str) using ==.
Fixes: c6e536e384 ("build: add more implementers IDs and PNs for ARM")
Cc: stable@dpdk.org
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Rename the cross files for meson compilation from having linuxapp
in the name to just linux in the name.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Enable native/cross compiling for Cortex-A55 and Cortex-A76 on meson.
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
pcap has historically shipped a custom pcap-config binary tool which
does the job of pkg-config. It was never compatible with cross
compilation.
Meson uses it when using dependency(), which then means cross
compilation fails.
Set pcap-config to empty in the meson cross compilation files so
that Meson will not use it, and add a fallback in case
dependency() fails.
libpcap 1.9.0 finally ships a pkg-config file so everything will
work out of the box in the future.
Signed-off-by: Luca Boccassi <luca.boccassi@microsoft.com>
Rather than relying on the target machine architecture, use the
size of a pointer from the compiler to determine if we are 64-bits
or not. This allows correct behaviour when you pass -m32 as a compile
option. It also allows us to use this value repeatedly throughout the
repo rather than continually testing for the sizeof(void*).
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Luca Boccassi <bluca@debian.org>
Acked-by: Luca Boccassi <bluca@debian.org>
This patch makes the configuration based on makefile and the
configuration based on meson to be the same.
Fixes: c6e536e384 ("build: add more implementers IDs and PNs for ARM")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
When running dpdk applications on cores whose ids are bigger
than original max_core setting, eal error as below:
EAL: Detected 104 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: invalid core list
-l CORELIST core indexes between 0 and 128
The fix is to increase max_core to 256 on arm64 platform.
Fixes: b3ce00e5 ("mk: introduce ARMv8 architecture")
Cc: stable@dpdk.org
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Building on armv7a with meson currenctly fails:
/usr/lib/gcc/arm-linux-gnueabihf/8/include/arm_neon.h:10369:1: error:
inlining failed in call to always_inline ‘vld1q_s32’: target
specific option mismatch
Set -mfpu=neon on that architecture like the legacy makefiles do to fix
the issue.
Fixes: b1d48c4118 ("build: support ARM with meson")
Cc: stable@dpdk.org
Signed-off-by: Luca Boccassi <bluca@debian.org>
Acked-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
model, so all modules can leverage C11 atomic extension by enable this
option.
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
GCC version 4.8.5 does not pre-define __ARM_NEON. NEON is not
optional for ArmV8. Hence NEON related code can be enabled
when __aarch64__ is defined.
Bugzilla ID: 82
Cc: stable@dpdk.org
Reported-by: Raslan Darawsheh <rasland@mellanox.com>
Reported-by: Thomas F Herbert <therbert@redhat.com>
Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
By default, the DPAA2_USE_PHYS_IOVA setting with the make build-system
is "y", which is overridden to "n" in the config file specifically for
the arm64-dpaa2-linuxapp-gcc builds. The lack of this setting in meson
builds causes issues for 32-bit build, as the alternative code paths
have compiler warnings e.g. for i686 builds. Therefore we should align
the meson and make settings, setting the value to "true" by default and
overriding it to "false" for dpaa2-specific builds.
Fixes: 6ec78c2463 ("build: add meson support for dpaaX platforms")
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
This is to fix the unnecessary warning output, it is not consistent with
the configurations of other platforms.
WARNING: Cross file does not specify strip binary, result will not be
stripped.
Fixes: e53a5299d2 ("build: support vendor specific ARM cross builds")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Song Zhu <song.zhu@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Tested-by: Ali Alnubani <alialnu@mellanox.com>
The make based build system has crc+crypto instruction
support for the default arm64 build.
http://dpdk.org/browse/dpdk/tree/mk/machine/armv8a/rte.vars.mk#n31
This patch fixes the disparity with meson build flags for armv8.
As a bonus, This patch fixes the following errors with
ip_pipeline example application.
Assembler messages:
Error: selected processor does not support `crc32cx w3,w3,x0'
Fixes: c6e536e384 ("build: add more implementers IDs and PNs for ARM")
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Tested-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Meson reports the toolchain using cc.get_id and we can set RTE_TOOLCHAIN,
RTE_TOOLCHAIN_X in dpdk_conf so that it can be used by both x86 and arm.
Suggested-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
1) Add native PN option '-march=native' to allow automatic detection.
Set 'arm_force_native_march' to 'true' in config/arm/meson.build
to use native PN option.
2) Add implementer_pn option for part num selection in cross compile
3) Add known Arm cortex PN support
4) Add known implementers' IDs (use generic flags/archs by default)
5) Sync build options with config/common_armv8a_linuxapp
Signed-off-by: Herbert Guan <herbert.guan@arm.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Add various vendor specific cross build targets.
This can be verified by using linaro toolchain and running
meson build --cross-file config/arm/arm64_<cpu>_<platform>_<compiler>
In future more cross build targets can be added.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Added support for detecting march and mcpu by reading midr_el1 register.
The implementer, primary part number values read can be used to figure
out the underlying arm cpu.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Add files to enable compiling for ARM native/cross builds.
This can be tested by doing a cross-compile for armv8-a type using
the linaro gcc toolchain.
meson arm-build --cross-file aarch64_cross.txt
ninja -C arm-build
where aarch64_cross.txt contained the following
[binaries]
c = 'aarch64-linux-gnu-gcc'
cpp = 'aarch64-linux-gnu-cpp'
ar = 'aarch64-linux-gnu-ar'
[host_machine]
system = 'linux'
cpu_family = 'aarch64'
cpu = 'armv8-a'
endian = 'little'
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
