The base driver supports more NICs:
- i210 flashless
- i217
- i218
- i354
The new features are not automatically used by the DPDK PMD.
Signed-off-by: Intel
- The flags NETIF_F_HW_VLAN_* have been renamed to NETIF_F_HW_VLAN_CTAG_*.
See Linux commit f646968f8f7c624587de729115d802372b9063dd.
- The VLAN protocol must be specified.
See Linux commits 86a9bad3ab6b6f858fd4443b48738cabbb6d094c
and 80d5c3689b886308247da295a228a54df49a44f6.
Signed-off-by: Intel
The function rte_eth_dev_allocate() was called by rte_eth_dev_init().
In order to use it for non-pci devices, it is now in public API.
Signed-off-by: Intel
This type of pseudo-device is needed for ring and pcap PMDs.
They are compatible with whitelist and are initialized in rte_eal_init().
Signed-off-by: Intel
In case of multi-process application, the secondary process can initialize
the driver without configuring queues. In this case the Rx/Tx functions
were not initialized because it was only done in queue setup.
Fix by reproducing the same behaviour as in eth_ixgbe_dev_init().
Signed-off-by: Intel
In case of multi-process application, the secondary process can initialize
the driver without configuring queues. In this case the Rx/Tx functions
were not initialized because it was only done in queue setup.
Fix by reproducing the same behaviour as in eth_igb_dev_init().
Signed-off-by: Intel
rte_malloc try to allocate memzone blocks with a minimum size.
It it fails, it retries for a smaller size than the standard one.
It will really fail if it cannot allocate block of the requested size.
Signed-off-by: Intel
The pause instruction is part of SSE2 extensions.
Note that some compilers define _mm_pause as "rep; nop" instead of "pause".
For compatible processors, they are equivalent.
http://www.intel.com/Assets/PDF/manual/325383.pdf:
"
When executing a spin-wait loop, a Pentium 4 or Intel Xeon processor suffers
a severe performance penalty when exiting the loop because it detects a
possible memory order violation.
The PAUSE instruction provides a hint to the processor that the code sequence
is a spin-wait loop. The processor uses this hint to avoid the memory order
violation in most situations, which greatly improves processor performance.
"
Signed-off-by: Intel
