95a6b04f7d
'OCTEON TX' is the registered name. All other usages need to be fixed. Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Cavium, Inc
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*/
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#ifndef __OCTEONTX_FPAVF_H__
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#define __OCTEONTX_FPAVF_H__
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#include <rte_io.h>
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#include "octeontx_pool_logs.h"
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/* fpa pool Vendor ID and Device ID */
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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#define PCI_DEVICE_ID_OCTEONTX_FPA_VF 0xA053
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#define FPA_VF_MAX 32
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#define FPA_GPOOL_MASK (FPA_VF_MAX-1)
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#define FPA_GAURA_SHIFT 4
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/* FPA VF register offsets */
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#define FPA_VF_INT(x) (0x200ULL | ((x) << 22))
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#define FPA_VF_INT_W1S(x) (0x210ULL | ((x) << 22))
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#define FPA_VF_INT_ENA_W1S(x) (0x220ULL | ((x) << 22))
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#define FPA_VF_INT_ENA_W1C(x) (0x230ULL | ((x) << 22))
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#define FPA_VF_VHPOOL_AVAILABLE(vhpool) (0x04150 | ((vhpool)&0x0))
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#define FPA_VF_VHPOOL_THRESHOLD(vhpool) (0x04160 | ((vhpool)&0x0))
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#define FPA_VF_VHPOOL_START_ADDR(vhpool) (0x04200 | ((vhpool)&0x0))
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#define FPA_VF_VHPOOL_END_ADDR(vhpool) (0x04210 | ((vhpool)&0x0))
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#define FPA_VF_VHAURA_CNT(vaura) (0x20120 | ((vaura)&0xf)<<18)
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#define FPA_VF_VHAURA_CNT_ADD(vaura) (0x20128 | ((vaura)&0xf)<<18)
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#define FPA_VF_VHAURA_CNT_LIMIT(vaura) (0x20130 | ((vaura)&0xf)<<18)
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#define FPA_VF_VHAURA_CNT_THRESHOLD(vaura) (0x20140 | ((vaura)&0xf)<<18)
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#define FPA_VF_VHAURA_OP_ALLOC(vaura) (0x30000 | ((vaura)&0xf)<<18)
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#define FPA_VF_VHAURA_OP_FREE(vaura) (0x38000 | ((vaura)&0xf)<<18)
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#define FPA_VF_FREE_ADDRS_S(x, y, z) \
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((x) | (((y) & 0x1ff) << 3) | ((((z) & 1)) << 14))
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#define FPA_AURA_IDX(gpool) (gpool << FPA_GAURA_SHIFT)
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/* FPA VF register offsets from VF_BAR4, size 2 MByte */
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#define FPA_VF_MSIX_VEC_ADDR 0x00000
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#define FPA_VF_MSIX_VEC_CTL 0x00008
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#define FPA_VF_MSIX_PBA 0xF0000
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#define FPA_VF0_APERTURE_SHIFT 22
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#define FPA_AURA_SET_SIZE 16
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#define FPA_MAX_OBJ_SIZE (128 * 1024)
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#define OCTEONTX_FPAVF_BUF_OFFSET 128
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/*
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* In Cavium OCTEON TX SoC, all accesses to the device registers are
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* implicitly strongly ordered. So, the relaxed version of IO operation is
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* safe to use with out any IO memory barriers.
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*/
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#define fpavf_read64 rte_read64_relaxed
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#define fpavf_write64 rte_write64_relaxed
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/* ARM64 specific functions */
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#if defined(RTE_ARCH_ARM64)
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#define fpavf_load_pair(val0, val1, addr) ({ \
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asm volatile( \
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"ldp %x[x0], %x[x1], [%x[p1]]" \
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:[x0]"=r"(val0), [x1]"=r"(val1) \
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:[p1]"r"(addr) \
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); })
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#define fpavf_store_pair(val0, val1, addr) ({ \
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asm volatile( \
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"stp %x[x0], %x[x1], [%x[p1]]" \
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::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
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); })
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#else /* Un optimized functions for building on non arm64 arch */
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#define fpavf_load_pair(val0, val1, addr) \
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do { \
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val0 = rte_read64(addr); \
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val1 = rte_read64(((uint8_t *)addr) + 8); \
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} while (0)
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#define fpavf_store_pair(val0, val1, addr) \
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do { \
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rte_write64(val0, addr); \
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rte_write64(val1, (((uint8_t *)addr) + 8)); \
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} while (0)
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#endif
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uintptr_t
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octeontx_fpa_bufpool_create(unsigned int object_size, unsigned int object_count,
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unsigned int buf_offset, int node);
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int
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octeontx_fpavf_pool_set_range(uintptr_t handle, unsigned long memsz,
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void *memva, uint16_t gpool);
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int
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octeontx_fpa_bufpool_destroy(uintptr_t handle, int node);
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int
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octeontx_fpa_bufpool_block_size(uintptr_t handle);
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int
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octeontx_fpa_bufpool_free_count(uintptr_t handle);
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static __rte_always_inline uint8_t
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octeontx_fpa_bufpool_gpool(uintptr_t handle)
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{
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return (uint8_t)handle & FPA_GPOOL_MASK;
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}
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static __rte_always_inline uint16_t
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octeontx_fpa_bufpool_gaura(uintptr_t handle)
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{
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return octeontx_fpa_bufpool_gpool(handle) << FPA_GAURA_SHIFT;
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}
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#endif /* __OCTEONTX_FPAVF_H__ */
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