701 lines
22 KiB
C
701 lines
22 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXGBE_ETHDEV_H_
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#define _IXGBE_ETHDEV_H_
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#include "base/ixgbe_dcb.h"
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#include "base/ixgbe_dcb_82599.h"
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#include "base/ixgbe_dcb_82598.h"
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#include "ixgbe_bypass.h"
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#include <rte_time.h>
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#include <rte_hash.h>
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/* need update link, bit flag */
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#define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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#define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
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#define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
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#define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
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/*
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* Defines that were not part of ixgbe_type.h as they are not used by the
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* FreeBSD driver.
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*/
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#define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
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#define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
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#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
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#define IXGBE_RXDADV_ERR_CKSUM_BIT 30
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#define IXGBE_RXDADV_ERR_CKSUM_MSK 3
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#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
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#define IXGBE_NB_STAT_MAPPING_REGS 32
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#define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
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#define IXGBE_VFTA_SIZE 128
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#define IXGBE_VLAN_TAG_SIZE 4
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#define IXGBE_MAX_RX_QUEUE_NUM 128
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#define IXGBE_MAX_INTR_QUEUE_NUM 15
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#define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
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#define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
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#define IXGBE_NONE_MODE_TX_NB_QUEUES 64
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#ifndef NBBY
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#define NBBY 8 /* number of bits in a byte */
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#endif
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#define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
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/* EITR Inteval is in 2048ns uinits for 1G and 10G link */
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#define IXGBE_EITR_INTERVAL_UNIT_NS 2048
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#define IXGBE_EITR_ITR_INT_SHIFT 3
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#define IXGBE_EITR_INTERVAL_US(us) \
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(((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
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IXGBE_EITR_ITR_INT_MASK)
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/* Loopback operation modes */
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/* 82599 specific loopback operation types */
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#define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
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#define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
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#define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
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#define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
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#define IXGBE_RTTBCNRC_RF_INT_MASK_M \
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(IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
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#define IXGBE_MAX_QUEUE_NUM_PER_VF 8
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#define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
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#define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
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#define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
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#define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
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#define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
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#define IXGBE_ETQF_SHIFT 16
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#define IXGBE_ETQF_UP_EN 0x00080000
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#define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
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#define IXGBE_ETQF_MAX_PRI 7
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#define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
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#define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
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#define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
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#define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
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#define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
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#define IXGBE_L34T_IMIR_LLI 0x00100000
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#define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
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#define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
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#define IXGBE_5TUPLE_MAX_PRI 7
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#define IXGBE_5TUPLE_MIN_PRI 1
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#define IXGBE_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_IPV6_EX | \
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ETH_RSS_IPV6_TCP_EX | \
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ETH_RSS_IPV6_UDP_EX)
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#define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
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#define IXGBE_VF_MAXMSIVECTOR 1
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#define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
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#define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
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#define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
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#define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
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#define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
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#define IXGBE_MAX_L2_TN_FILTER_NUM 128
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/*
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* Information about the fdir mode.
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*/
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struct ixgbe_hw_fdir_mask {
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uint16_t vlan_tci_mask;
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uint32_t src_ipv4_mask;
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uint32_t dst_ipv4_mask;
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uint16_t src_ipv6_mask;
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uint16_t dst_ipv6_mask;
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uint16_t src_port_mask;
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uint16_t dst_port_mask;
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uint16_t flex_bytes_mask;
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uint8_t mac_addr_byte_mask;
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uint32_t tunnel_id_mask;
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uint8_t tunnel_type_mask;
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};
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struct ixgbe_fdir_filter {
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TAILQ_ENTRY(ixgbe_fdir_filter) entries;
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union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
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uint32_t fdirflags; /* drop or forward */
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uint32_t fdirhash; /* hash value for fdir */
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uint8_t queue; /* assigned rx queue */
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};
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/* list of fdir filters */
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TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
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struct ixgbe_fdir_rule {
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struct ixgbe_hw_fdir_mask mask;
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union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
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bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
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bool b_mask; /* If TRUE, mask has meaning. */
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enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
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uint32_t fdirflags; /* drop or forward */
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uint32_t soft_id; /* an unique value for this rule */
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uint8_t queue; /* assigned rx queue */
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};
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struct ixgbe_hw_fdir_info {
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struct ixgbe_hw_fdir_mask mask;
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uint8_t flex_bytes_offset;
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uint16_t collision;
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uint16_t free;
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uint16_t maxhash;
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uint8_t maxlen;
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uint64_t add;
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uint64_t remove;
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uint64_t f_add;
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uint64_t f_remove;
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struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
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/* store the pointers of the filters, index is the hash value. */
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struct ixgbe_fdir_filter **hash_map;
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struct rte_hash *hash_handle; /* cuckoo hash handler */
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bool mask_added; /* If already got mask from consistent filter */
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};
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/* structure for interrupt relative data */
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struct ixgbe_interrupt {
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uint32_t flags;
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uint32_t mask;
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/*to save original mask during delayed handler */
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uint32_t mask_original;
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};
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struct ixgbe_stat_mapping_registers {
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uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
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uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
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};
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struct ixgbe_vfta {
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uint32_t vfta[IXGBE_VFTA_SIZE];
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};
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struct ixgbe_hwstrip {
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uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
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};
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/*
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* VF data which used by PF host only
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*/
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#define IXGBE_MAX_VF_MC_ENTRIES 30
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#define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
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#define IXGBE_MAX_UTA 128
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struct ixgbe_uta_info {
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uint8_t uc_filter_type;
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uint16_t uta_in_use;
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uint32_t uta_shadow[IXGBE_MAX_UTA];
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};
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#define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
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struct ixgbe_mirror_info {
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struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
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/**< store PF mirror rules configuration*/
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};
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struct ixgbe_vf_info {
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uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
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uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
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uint16_t num_vf_mc_hashes;
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uint16_t default_vf_vlan_id;
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uint16_t vlans_enabled;
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bool clear_to_send;
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uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
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uint16_t vlan_count;
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uint8_t spoofchk_enabled;
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uint8_t api_version;
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};
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/*
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* Possible l4type of 5tuple filters.
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*/
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enum ixgbe_5tuple_protocol {
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IXGBE_FILTER_PROTOCOL_TCP = 0,
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IXGBE_FILTER_PROTOCOL_UDP,
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IXGBE_FILTER_PROTOCOL_SCTP,
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IXGBE_FILTER_PROTOCOL_NONE,
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};
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TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
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struct ixgbe_5tuple_filter_info {
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uint32_t dst_ip;
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uint32_t src_ip;
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uint16_t dst_port;
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uint16_t src_port;
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enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
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uint8_t priority; /* seven levels (001b-111b), 111b is highest,
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used when more than one filter matches. */
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uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
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src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
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dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
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src_port_mask:1, /* if mask is 1b, do not compare src port. */
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proto_mask:1; /* if mask is 1b, do not compare protocol. */
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};
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/* 5tuple filter structure */
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struct ixgbe_5tuple_filter {
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TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
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uint16_t index; /* the index of 5tuple filter */
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struct ixgbe_5tuple_filter_info filter_info;
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uint16_t queue; /* rx queue assigned to */
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};
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#define IXGBE_5TUPLE_ARRAY_SIZE \
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(RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
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(sizeof(uint32_t) * NBBY))
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struct ixgbe_ethertype_filter {
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uint16_t ethertype;
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uint32_t etqf;
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uint32_t etqs;
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/**
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* If this filter is added by configuration,
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* it should not be removed.
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*/
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bool conf;
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};
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/*
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* Structure to store filters' info.
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*/
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struct ixgbe_filter_info {
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uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
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/* store used ethertype filters*/
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struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
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/* Bit mask for every used 5tuple filter */
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uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
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struct ixgbe_5tuple_filter_list fivetuple_list;
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/* store the SYN filter info */
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uint32_t syn_info;
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};
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struct ixgbe_l2_tn_key {
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enum rte_eth_tunnel_type l2_tn_type;
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uint32_t tn_id;
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};
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struct ixgbe_l2_tn_filter {
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TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
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struct ixgbe_l2_tn_key key;
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uint32_t pool;
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};
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TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
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struct ixgbe_l2_tn_info {
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struct ixgbe_l2_tn_filter_list l2_tn_list;
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struct ixgbe_l2_tn_filter **hash_map;
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struct rte_hash *hash_handle;
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bool e_tag_en; /* e-tag enabled */
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bool e_tag_fwd_en; /* e-tag based forwarding enabled */
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bool e_tag_ether_type; /* ether type for e-tag */
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};
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struct rte_flow {
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enum rte_filter_type filter_type;
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void *rule;
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};
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/* ntuple filter list structure */
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struct ixgbe_ntuple_filter_ele {
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TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
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struct rte_eth_ntuple_filter filter_info;
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};
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/* ethertype filter list structure */
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struct ixgbe_ethertype_filter_ele {
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TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
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struct rte_eth_ethertype_filter filter_info;
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};
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/* syn filter list structure */
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struct ixgbe_eth_syn_filter_ele {
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TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
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struct rte_eth_syn_filter filter_info;
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};
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/* fdir filter list structure */
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struct ixgbe_fdir_rule_ele {
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TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
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struct ixgbe_fdir_rule filter_info;
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};
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/* l2_tunnel filter list structure */
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struct ixgbe_eth_l2_tunnel_conf_ele {
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TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
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struct rte_eth_l2_tunnel_conf filter_info;
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};
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/* ixgbe_flow memory list structure */
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struct ixgbe_flow_mem {
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TAILQ_ENTRY(ixgbe_flow_mem) entries;
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struct rte_flow *flow;
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};
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TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
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struct ixgbe_ntuple_filter_list filter_ntuple_list;
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TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
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struct ixgbe_ethertype_filter_list filter_ethertype_list;
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TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
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struct ixgbe_syn_filter_list filter_syn_list;
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TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
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struct ixgbe_fdir_rule_filter_list filter_fdir_list;
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TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
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struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
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TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
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struct ixgbe_flow_mem_list ixgbe_flow_list;
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/*
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* Statistics counters collected by the MACsec
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*/
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struct ixgbe_macsec_stats {
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/* TX port statistics */
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uint64_t out_pkts_untagged;
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uint64_t out_pkts_encrypted;
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uint64_t out_pkts_protected;
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uint64_t out_octets_encrypted;
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uint64_t out_octets_protected;
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/* RX port statistics */
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uint64_t in_pkts_untagged;
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uint64_t in_pkts_badtag;
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uint64_t in_pkts_nosci;
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uint64_t in_pkts_unknownsci;
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uint64_t in_octets_decrypted;
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uint64_t in_octets_validated;
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/* RX SC statistics */
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uint64_t in_pkts_unchecked;
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uint64_t in_pkts_delayed;
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uint64_t in_pkts_late;
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/* RX SA statistics */
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uint64_t in_pkts_ok;
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uint64_t in_pkts_invalid;
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uint64_t in_pkts_notvalid;
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uint64_t in_pkts_unusedsa;
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uint64_t in_pkts_notusingsa;
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};
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/*
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* Structure to store private data for each driver instance (for each port).
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*/
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struct ixgbe_adapter {
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struct ixgbe_hw hw;
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struct ixgbe_hw_stats stats;
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struct ixgbe_macsec_stats macsec_stats;
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struct ixgbe_hw_fdir_info fdir;
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struct ixgbe_interrupt intr;
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struct ixgbe_stat_mapping_registers stat_mappings;
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struct ixgbe_vfta shadow_vfta;
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struct ixgbe_hwstrip hwstrip;
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struct ixgbe_dcb_config dcb_config;
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struct ixgbe_mirror_info mr_data;
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struct ixgbe_vf_info *vfdata;
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struct ixgbe_uta_info uta_info;
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#ifdef RTE_NIC_BYPASS
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struct ixgbe_bypass_info bps;
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#endif /* RTE_NIC_BYPASS */
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struct ixgbe_filter_info filter;
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struct ixgbe_l2_tn_info l2_tn;
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bool rx_bulk_alloc_allowed;
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bool rx_vec_allowed;
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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};
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#define IXGBE_DEV_TO_PCI(eth_dev) \
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RTE_DEV_TO_PCI((eth_dev)->device)
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#define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
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(&((struct ixgbe_adapter *)adapter)->hw)
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#define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
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(&((struct ixgbe_adapter *)adapter)->stats)
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#define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
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(&((struct ixgbe_adapter *)adapter)->macsec_stats)
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#define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
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(&((struct ixgbe_adapter *)adapter)->intr)
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#define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
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(&((struct ixgbe_adapter *)adapter)->fdir)
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#define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
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(&((struct ixgbe_adapter *)adapter)->stat_mappings)
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#define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->shadow_vfta)
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#define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
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(&((struct ixgbe_adapter *)adapter)->hwstrip)
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#define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
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(&((struct ixgbe_adapter *)adapter)->dcb_config)
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#define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->vfdata)
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#define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->mr_data)
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#define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->uta_info)
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#define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
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(&((struct ixgbe_adapter *)adapter)->filter)
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#define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
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(&((struct ixgbe_adapter *)adapter)->l2_tn)
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/*
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* RX/TX function prototypes
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*/
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void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
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void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
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void ixgbe_dev_rx_queue_release(void *rxq);
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void ixgbe_dev_tx_queue_release(void *txq);
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int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
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int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
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void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
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int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
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int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_rxq_info *qinfo);
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void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_txq_info *qinfo);
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int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
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void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
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void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
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uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
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uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
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uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
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uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
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bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
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int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
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struct rte_eth_ntuple_filter *filter,
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bool add);
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int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
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struct rte_eth_ethertype_filter *filter,
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bool add);
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int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
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struct rte_eth_syn_filter *filter,
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bool add);
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int
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ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
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struct rte_eth_l2_tunnel_conf *l2_tunnel,
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bool restore);
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int
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ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
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struct rte_eth_l2_tunnel_conf *l2_tunnel);
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void ixgbe_filterlist_flush(void);
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/*
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* Flow director function prototypes
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*/
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int ixgbe_fdir_configure(struct rte_eth_dev *dev);
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int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
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int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
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struct ixgbe_fdir_rule *rule,
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bool del, bool update);
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void ixgbe_configure_dcb(struct rte_eth_dev *dev);
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/*
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* misc function prototypes
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*/
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void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
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void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
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void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
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void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
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int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
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uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
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int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
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enum rte_filter_op filter_op, void *arg);
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void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
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int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
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extern const struct rte_flow_ops ixgbe_flow_ops;
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void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
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void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
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void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
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int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
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int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
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int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
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static inline int
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ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
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uint16_t ethertype)
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{
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int i;
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for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
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if (filter_info->ethertype_filters[i].ethertype == ethertype &&
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(filter_info->ethertype_mask & (1 << i)))
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return i;
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}
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return -1;
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}
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static inline int
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ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
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struct ixgbe_ethertype_filter *ethertype_filter)
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{
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int i;
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for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
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if (!(filter_info->ethertype_mask & (1 << i))) {
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filter_info->ethertype_mask |= 1 << i;
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filter_info->ethertype_filters[i].ethertype =
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ethertype_filter->ethertype;
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filter_info->ethertype_filters[i].etqf =
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ethertype_filter->etqf;
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filter_info->ethertype_filters[i].etqs =
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ethertype_filter->etqs;
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filter_info->ethertype_filters[i].conf =
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ethertype_filter->conf;
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return i;
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}
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}
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return -1;
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}
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static inline int
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ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
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uint8_t idx)
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|
{
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|
if (idx >= IXGBE_MAX_ETQF_FILTERS)
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return -1;
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|
filter_info->ethertype_mask &= ~(1 << idx);
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filter_info->ethertype_filters[idx].ethertype = 0;
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filter_info->ethertype_filters[idx].etqf = 0;
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filter_info->ethertype_filters[idx].etqs = 0;
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filter_info->ethertype_filters[idx].etqs = FALSE;
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return idx;
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}
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#endif /* _IXGBE_ETHDEV_H_ */
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