834d99f388
Add PPD (PCIe Port Definition) status check for SPR (Sapphire Rapids). Note that NTB on SPR has the same device id with that on ICX, while the field offsets of PPD Control Register are different. Here, we use the PCI device revision id to distinguish the HW platform (ICX/SPR) and check the Port Config Status and Port Definition accordingly. +---------------------------+--------------------+--------------------+ | Fields | Bit Range (on ICX) | Bit Range (on SPR) | +---------------------------+--------------------+--------------------+ | Port Configuration Status | 12 | 14 | | Port Definition | 9:8 | 10:8 | +---------------------------+--------------------+--------------------+ Signed-off-by: Junfeng Guo <junfeng.guo@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
119 lines
4.2 KiB
C
119 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation.
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*/
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#ifndef _NTB_HW_INTEL_H_
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#define _NTB_HW_INTEL_H_
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/* Supported PCI device revision ID range for ICX */
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#define NTB_PCI_DEV_REVISION_ICX_MIN 0x02
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#define NTB_PCI_DEV_REVISION_ICX_MAX 0x0F
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#define NTB_PCI_DEV_REVISION_ID_REG 0x08
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#define NTB_PCI_DEV_REVISION_ID_LEN 1
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/* Ntb control and link status */
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#define NTB_CTL_CFG_LOCK 1
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#define NTB_CTL_DISABLE 2
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#define NTB_CTL_S2P_BAR2_SNOOP (1 << 2)
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#define NTB_CTL_P2S_BAR2_SNOOP (1 << 4)
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#define NTB_CTL_S2P_BAR4_SNOOP (1 << 6)
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#define NTB_CTL_P2S_BAR4_SNOOP (1 << 8)
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#define NTB_CTL_S2P_BAR5_SNOOP (1 << 12)
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#define NTB_CTL_P2S_BAR5_SNOOP (1 << 14)
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#define NTB_LNK_STA_ACTIVE_BIT 0x2000
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#define NTB_LNK_STA_SPEED_MASK 0x000f
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#define NTB_LNK_STA_WIDTH_MASK 0x03f0
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
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/* Intel Xeon hardware */
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#define XEON_IMBAR1SZ_OFFSET 0x00d0
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#define XEON_IMBAR2SZ_OFFSET 0x00d1
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#define XEON_EMBAR1SZ_OFFSET 0x00d2
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#define XEON_EMBAR2SZ_OFFSET 0x00d3
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#define XEON_DEVCTRL_OFFSET 0x0098
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#define XEON_DEVSTS_OFFSET 0x009a
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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#define XEON_GEN3_LINK_STATUS_OFFSET 0x01a2
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/* Link status and PPD are in MMIO but not config space for Gen4 NTB */
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#define XEON_GEN4_PPD0_OFFSET 0xb0d4
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#define XEON_GEN4_PPD1_OFFSET 0xb4c0
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#define XEON_GEN4_LINK_CTRL_OFFSET 0xb050
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#define XEON_GEN4_LINK_STATUS_OFFSET 0xb052
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#define XEON_GEN4_LINK_CTRL_LINK_DIS 0x0010
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#define XEON_NTBCNTL_OFFSET 0x0000
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#define XEON_BAR_INTERVAL_OFFSET 0x0010
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#define XEON_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
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#define XEON_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
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#define XEON_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
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#define XEON_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
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#define XEON_GEN4_XBASEIDX_INTERVAL 0x0002
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#define XEON_GEN4_IM1XBASEIDX_OFFSET 0x0074
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#define XEON_GEN4_IM2XBASEIDX_OFFSET 0x0076
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#define XEON_IM_INT_STATUS_OFFSET 0x0040
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#define XEON_IM_INT_DISABLE_OFFSET 0x0048
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#define XEON_IM_SPAD_OFFSET 0x0080 /* SPAD */
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#define XEON_GEN3_B2B_SPAD_OFFSET 0x0180 /* GEN3 B2B SPAD */
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#define XEON_GEN4_B2B_SPAD_OFFSET 0x8080 /* GEN4 B2B SPAD */
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#define XEON_USMEMMISS_OFFSET 0x0070
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#define XEON_GEN3_INTVEC_OFFSET 0x00d0
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#define XEON_GEN4_INTVEC_OFFSET 0x0050
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#define XEON_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
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#define XEON_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
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#define XEON_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
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#define XEON_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
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#define XEON_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
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#define XEON_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
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#define XEON_EM_INT_STATUS_OFFSET 0x4040
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#define XEON_EM_INT_DISABLE_OFFSET 0x4048
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#define XEON_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
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#define XEON_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
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#define XEON_SPCICMD_OFFSET 0x4504 /* SPCICMD */
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#define XEON_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
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#define XEON_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
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#define XEON_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
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#define XEON_PPD_OFFSET 0x00d4
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#define XEON_PPD_CONN_MASK 0x03
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#define XEON_PPD_CONN_TRANSPARENT 0x00
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#define XEON_PPD_CONN_B2B 0x01
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#define XEON_PPD_CONN_RP 0x02
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#define XEON_PPD_DEV_MASK 0x10
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#define XEON_PPD_DEV_USD 0x00
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#define XEON_PPD_DEV_DSD 0x10
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#define XEON_PPD_SPLIT_BAR_MASK 0x40
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#define XEON_GEN4_PPD_CONN_MASK 0x0300
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#define XEON_GEN4_PPD_CONN_B2B 0x0200
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#define XEON_GEN4_PPD_DEV_MASK 0x1000
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#define XEON_GEN4_PPD_DEV_DSD 0x1000
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#define XEON_GEN4_PPD_DEV_USD 0x0000
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#define XEON_GEN4_PPD_LINKTRN 0x0008
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#define XEON_GEN4_SLOTSTS 0xb05a
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#define XEON_GEN4_SLOTSTS_DLLSCS 0x100
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#define XEON_SPR_PPD_CONN_MASK 0x0700
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#define XEON_SPR_PPD_CONN_B2B 0x0200
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#define XEON_SPR_PPD_DEV_MASK 0x4000
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#define XEON_SPR_PPD_DEV_DSD 0x4000
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#define XEON_SPR_PPD_DEV_USD 0x0000
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#define XEON_MW_COUNT 2
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#define XEON_DB_COUNT 32
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#define XEON_DB_LINK 32
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#define XEON_DB_LINK_BIT (1ULL << XEON_DB_LINK)
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#define XEON_DB_MSIX_VECTOR_COUNT 33
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#define XEON_DB_MSIX_VECTOR_SHIFT 1
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#define XEON_DB_TOTAL_SHIFT 33
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#define XEON_SPAD_COUNT 16
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extern const struct ntb_dev_ops intel_ntb_ops;
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#endif /* _NTB_HW_INTEL_H_ */
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