Jerin Jacob 6e757e6942 config: clean cache line size selection scheme ... by default, all the targets will be configured with the 64-byte cache line size, targets which have different cache line size can be overridden through target specific config file. Selected ThunderX and power8 as CONFIG_RTE_CACHE_LINE_SIZE=128 targets based on existing configuration. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>		2016-02-11 12:45:35 +01:00
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arm	config: clean cache line size selection scheme	2016-02-11 12:45:35 +01:00
arm64	mk: introduce ARMv8 architecture	2015-11-18 22:44:01 +01:00
i686	eal: factorize x86 headers	2014-11-05 22:20:24 +01:00
ppc_64	config: clean cache line size selection scheme	2016-02-11 12:45:35 +01:00
tile	eal/tile: add initial TILE-Gx support	2015-07-13 16:15:52 +02:00
x86_64	eal: factorize x86 headers	2014-11-05 22:20:24 +01:00
x86_x32	mk: support x32 ABI	2015-02-18 20:26:33 +01:00