36ea36efb4
Declare dst as type uint32_t instead of uint64_t, otherwise, we will get
a random upper 32 bit feature bits, as the following io port read reads
lower 32 bit only. It could lead a feature bits that include VIRTIO_F_VERSION_1
(the 32th bit) for legacy virtio, which is obviously wrong.
Fixes: b8f04520ad
("virtio: use PCI ioport API")
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Acked-by: Jianfeng Tan <jianfeng.tan@intel.com>
Reviewed-by: David Marchand <david.marchand@6wind.com>
667 lines
16 KiB
C
667 lines
16 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#ifdef RTE_EXEC_ENV_LINUXAPP
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#include <dirent.h>
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#include <fcntl.h>
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#endif
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#include "virtio_pci.h"
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#include "virtio_logs.h"
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#include "virtqueue.h"
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/*
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* Following macros are derived from linux/pci_regs.h, however,
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* we can't simply include that header here, as there is no such
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* file for non-Linux platform.
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*/
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#define PCI_CAPABILITY_LIST 0x34
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#define PCI_CAP_ID_VNDR 0x09
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/*
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* The remaining space is defined by each driver as the per-driver
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* configuration space.
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*/
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#define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
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static void
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legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
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void *dst, int length)
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{
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rte_eal_pci_ioport_read(&hw->io, dst, length,
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VIRTIO_PCI_CONFIG(hw) + offset);
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}
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static void
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legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
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const void *src, int length)
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{
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rte_eal_pci_ioport_write(&hw->io, src, length,
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VIRTIO_PCI_CONFIG(hw) + offset);
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}
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static uint64_t
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legacy_get_features(struct virtio_hw *hw)
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{
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uint32_t dst;
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rte_eal_pci_ioport_read(&hw->io, &dst, 4, VIRTIO_PCI_HOST_FEATURES);
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return dst;
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}
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static void
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legacy_set_features(struct virtio_hw *hw, uint64_t features)
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{
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if ((features >> 32) != 0) {
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PMD_DRV_LOG(ERR,
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"only 32 bit features are allowed for legacy virtio!");
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return;
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}
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rte_eal_pci_ioport_write(&hw->io, &features, 4,
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VIRTIO_PCI_GUEST_FEATURES);
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}
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static uint8_t
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legacy_get_status(struct virtio_hw *hw)
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{
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uint8_t dst;
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rte_eal_pci_ioport_read(&hw->io, &dst, 1, VIRTIO_PCI_STATUS);
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return dst;
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}
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static void
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legacy_set_status(struct virtio_hw *hw, uint8_t status)
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{
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rte_eal_pci_ioport_write(&hw->io, &status, 1, VIRTIO_PCI_STATUS);
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}
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static void
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legacy_reset(struct virtio_hw *hw)
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{
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legacy_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
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}
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static uint8_t
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legacy_get_isr(struct virtio_hw *hw)
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{
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uint8_t dst;
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rte_eal_pci_ioport_read(&hw->io, &dst, 1, VIRTIO_PCI_ISR);
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return dst;
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}
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/* Enable one vector (0) for Link State Intrerrupt */
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static uint16_t
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legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
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{
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uint16_t dst;
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rte_eal_pci_ioport_write(&hw->io, &vec, 2, VIRTIO_MSI_CONFIG_VECTOR);
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rte_eal_pci_ioport_read(&hw->io, &dst, 2, VIRTIO_MSI_CONFIG_VECTOR);
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return dst;
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}
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static uint16_t
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legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
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{
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uint16_t dst;
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rte_eal_pci_ioport_write(&hw->io, &queue_id, 2, VIRTIO_PCI_QUEUE_SEL);
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rte_eal_pci_ioport_read(&hw->io, &dst, 2, VIRTIO_PCI_QUEUE_NUM);
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return dst;
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}
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static void
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legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
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{
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uint32_t src;
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rte_eal_pci_ioport_write(&hw->io, &vq->vq_queue_index, 2,
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VIRTIO_PCI_QUEUE_SEL);
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src = vq->mz->phys_addr >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
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rte_eal_pci_ioport_write(&hw->io, &src, 4, VIRTIO_PCI_QUEUE_PFN);
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}
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static void
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legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
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{
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uint32_t src = 0;
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rte_eal_pci_ioport_write(&hw->io, &vq->vq_queue_index, 2,
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VIRTIO_PCI_QUEUE_SEL);
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rte_eal_pci_ioport_write(&hw->io, &src, 4, VIRTIO_PCI_QUEUE_PFN);
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}
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static void
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legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
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{
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rte_eal_pci_ioport_write(&hw->io, &vq->vq_queue_index, 2,
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VIRTIO_PCI_QUEUE_NOTIFY);
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}
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#ifdef RTE_EXEC_ENV_LINUXAPP
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static int
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legacy_virtio_has_msix(const struct rte_pci_addr *loc)
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{
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DIR *d;
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char dirname[PATH_MAX];
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snprintf(dirname, sizeof(dirname),
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SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/msi_irqs",
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loc->domain, loc->bus, loc->devid, loc->function);
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d = opendir(dirname);
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if (d)
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closedir(d);
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return d != NULL;
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}
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#else
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static int
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legacy_virtio_has_msix(const struct rte_pci_addr *loc __rte_unused)
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{
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/* nic_uio does not enable interrupts, return 0 (false). */
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return 0;
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}
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#endif
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static int
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legacy_virtio_resource_init(struct rte_pci_device *pci_dev,
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struct virtio_hw *hw)
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{
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if (rte_eal_pci_ioport_map(pci_dev, 0, &hw->io) < 0)
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return -1;
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if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UNKNOWN)
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pci_dev->driver->drv_flags |= RTE_PCI_DRV_INTR_LSC;
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else
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pci_dev->driver->drv_flags &= ~RTE_PCI_DRV_INTR_LSC;
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return 0;
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}
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static const struct virtio_pci_ops legacy_ops = {
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.read_dev_cfg = legacy_read_dev_config,
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.write_dev_cfg = legacy_write_dev_config,
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.reset = legacy_reset,
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.get_status = legacy_get_status,
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.set_status = legacy_set_status,
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.get_features = legacy_get_features,
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.set_features = legacy_set_features,
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.get_isr = legacy_get_isr,
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.set_config_irq = legacy_set_config_irq,
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.get_queue_num = legacy_get_queue_num,
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.setup_queue = legacy_setup_queue,
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.del_queue = legacy_del_queue,
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.notify_queue = legacy_notify_queue,
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};
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static inline uint8_t
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io_read8(uint8_t *addr)
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{
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return *(volatile uint8_t *)addr;
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}
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static inline void
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io_write8(uint8_t val, uint8_t *addr)
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{
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*(volatile uint8_t *)addr = val;
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}
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static inline uint16_t
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io_read16(uint16_t *addr)
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{
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return *(volatile uint16_t *)addr;
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}
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static inline void
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io_write16(uint16_t val, uint16_t *addr)
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{
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*(volatile uint16_t *)addr = val;
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}
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static inline uint32_t
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io_read32(uint32_t *addr)
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{
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return *(volatile uint32_t *)addr;
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}
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static inline void
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io_write32(uint32_t val, uint32_t *addr)
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{
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*(volatile uint32_t *)addr = val;
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}
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static inline void
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io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
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{
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io_write32(val & ((1ULL << 32) - 1), lo);
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io_write32(val >> 32, hi);
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}
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static void
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modern_read_dev_config(struct virtio_hw *hw, size_t offset,
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void *dst, int length)
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{
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int i;
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uint8_t *p;
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uint8_t old_gen, new_gen;
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do {
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old_gen = io_read8(&hw->common_cfg->config_generation);
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p = dst;
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for (i = 0; i < length; i++)
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*p++ = io_read8((uint8_t *)hw->dev_cfg + offset + i);
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new_gen = io_read8(&hw->common_cfg->config_generation);
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} while (old_gen != new_gen);
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}
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static void
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modern_write_dev_config(struct virtio_hw *hw, size_t offset,
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const void *src, int length)
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{
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int i;
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const uint8_t *p = src;
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for (i = 0; i < length; i++)
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io_write8(*p++, (uint8_t *)hw->dev_cfg + offset + i);
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}
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static uint64_t
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modern_get_features(struct virtio_hw *hw)
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{
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uint32_t features_lo, features_hi;
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io_write32(0, &hw->common_cfg->device_feature_select);
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features_lo = io_read32(&hw->common_cfg->device_feature);
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io_write32(1, &hw->common_cfg->device_feature_select);
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features_hi = io_read32(&hw->common_cfg->device_feature);
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return ((uint64_t)features_hi << 32) | features_lo;
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}
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static void
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modern_set_features(struct virtio_hw *hw, uint64_t features)
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{
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io_write32(0, &hw->common_cfg->guest_feature_select);
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io_write32(features & ((1ULL << 32) - 1),
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&hw->common_cfg->guest_feature);
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io_write32(1, &hw->common_cfg->guest_feature_select);
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io_write32(features >> 32,
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&hw->common_cfg->guest_feature);
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}
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static uint8_t
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modern_get_status(struct virtio_hw *hw)
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{
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return io_read8(&hw->common_cfg->device_status);
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}
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static void
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modern_set_status(struct virtio_hw *hw, uint8_t status)
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{
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io_write8(status, &hw->common_cfg->device_status);
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}
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static void
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modern_reset(struct virtio_hw *hw)
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{
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modern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
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modern_get_status(hw);
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}
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static uint8_t
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modern_get_isr(struct virtio_hw *hw)
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{
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return io_read8(hw->isr);
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}
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static uint16_t
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modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
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{
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io_write16(vec, &hw->common_cfg->msix_config);
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return io_read16(&hw->common_cfg->msix_config);
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}
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static uint16_t
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modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
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{
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io_write16(queue_id, &hw->common_cfg->queue_select);
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return io_read16(&hw->common_cfg->queue_size);
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}
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static void
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modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
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{
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uint64_t desc_addr, avail_addr, used_addr;
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uint16_t notify_off;
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desc_addr = vq->mz->phys_addr;
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avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
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used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
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ring[vq->vq_nentries]),
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VIRTIO_PCI_VRING_ALIGN);
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io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
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io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
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&hw->common_cfg->queue_desc_hi);
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io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
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&hw->common_cfg->queue_avail_hi);
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io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
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&hw->common_cfg->queue_used_hi);
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notify_off = io_read16(&hw->common_cfg->queue_notify_off);
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vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
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notify_off * hw->notify_off_multiplier);
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io_write16(1, &hw->common_cfg->queue_enable);
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PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
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PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
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PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
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PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
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PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
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vq->notify_addr, notify_off);
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}
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static void
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modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
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{
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io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
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io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
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&hw->common_cfg->queue_desc_hi);
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io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
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&hw->common_cfg->queue_avail_hi);
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io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
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&hw->common_cfg->queue_used_hi);
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io_write16(0, &hw->common_cfg->queue_enable);
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}
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static void
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modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
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{
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io_write16(1, vq->notify_addr);
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}
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static const struct virtio_pci_ops modern_ops = {
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.read_dev_cfg = modern_read_dev_config,
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.write_dev_cfg = modern_write_dev_config,
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.reset = modern_reset,
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.get_status = modern_get_status,
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.set_status = modern_set_status,
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.get_features = modern_get_features,
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.set_features = modern_set_features,
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.get_isr = modern_get_isr,
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.set_config_irq = modern_set_config_irq,
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.get_queue_num = modern_get_queue_num,
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.setup_queue = modern_setup_queue,
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.del_queue = modern_del_queue,
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.notify_queue = modern_notify_queue,
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};
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void
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vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
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void *dst, int length)
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{
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hw->vtpci_ops->read_dev_cfg(hw, offset, dst, length);
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}
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void
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vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
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const void *src, int length)
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{
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hw->vtpci_ops->write_dev_cfg(hw, offset, src, length);
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}
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uint64_t
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vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
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{
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uint64_t features;
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/*
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* Limit negotiated features to what the driver, virtqueue, and
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* host all support.
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*/
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features = host_features & hw->guest_features;
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hw->vtpci_ops->set_features(hw, features);
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return features;
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}
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void
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vtpci_reset(struct virtio_hw *hw)
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{
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hw->vtpci_ops->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
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/* flush status write */
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hw->vtpci_ops->get_status(hw);
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}
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void
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vtpci_reinit_complete(struct virtio_hw *hw)
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{
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vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
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}
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void
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vtpci_set_status(struct virtio_hw *hw, uint8_t status)
|
|
{
|
|
if (status != VIRTIO_CONFIG_STATUS_RESET)
|
|
status |= hw->vtpci_ops->get_status(hw);
|
|
|
|
hw->vtpci_ops->set_status(hw, status);
|
|
}
|
|
|
|
uint8_t
|
|
vtpci_get_status(struct virtio_hw *hw)
|
|
{
|
|
return hw->vtpci_ops->get_status(hw);
|
|
}
|
|
|
|
uint8_t
|
|
vtpci_isr(struct virtio_hw *hw)
|
|
{
|
|
return hw->vtpci_ops->get_isr(hw);
|
|
}
|
|
|
|
|
|
/* Enable one vector (0) for Link State Intrerrupt */
|
|
uint16_t
|
|
vtpci_irq_config(struct virtio_hw *hw, uint16_t vec)
|
|
{
|
|
return hw->vtpci_ops->set_config_irq(hw, vec);
|
|
}
|
|
|
|
static void *
|
|
get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
|
|
{
|
|
uint8_t bar = cap->bar;
|
|
uint32_t length = cap->length;
|
|
uint32_t offset = cap->offset;
|
|
uint8_t *base;
|
|
|
|
if (bar > 5) {
|
|
PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
|
|
return NULL;
|
|
}
|
|
|
|
if (offset + length < offset) {
|
|
PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
|
|
offset, length);
|
|
return NULL;
|
|
}
|
|
|
|
if (offset + length > dev->mem_resource[bar].len) {
|
|
PMD_INIT_LOG(ERR,
|
|
"invalid cap: overflows bar space: %u > %" PRIu64,
|
|
offset + length, dev->mem_resource[bar].len);
|
|
return NULL;
|
|
}
|
|
|
|
base = dev->mem_resource[bar].addr;
|
|
if (base == NULL) {
|
|
PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
|
|
return NULL;
|
|
}
|
|
|
|
return base + offset;
|
|
}
|
|
|
|
static int
|
|
virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
|
|
{
|
|
uint8_t pos;
|
|
struct virtio_pci_cap cap;
|
|
int ret;
|
|
|
|
if (rte_eal_pci_map_device(dev)) {
|
|
PMD_INIT_LOG(DEBUG, "failed to map pci device!");
|
|
return -1;
|
|
}
|
|
|
|
ret = rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
|
|
if (ret < 0) {
|
|
PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
|
|
return -1;
|
|
}
|
|
|
|
while (pos) {
|
|
ret = rte_eal_pci_read_config(dev, &cap, sizeof(cap), pos);
|
|
if (ret < 0) {
|
|
PMD_INIT_LOG(ERR,
|
|
"failed to read pci cap at pos: %x", pos);
|
|
break;
|
|
}
|
|
|
|
if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
|
|
PMD_INIT_LOG(DEBUG,
|
|
"[%2x] skipping non VNDR cap id: %02x",
|
|
pos, cap.cap_vndr);
|
|
goto next;
|
|
}
|
|
|
|
PMD_INIT_LOG(DEBUG,
|
|
"[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
|
|
pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
|
|
|
|
switch (cap.cfg_type) {
|
|
case VIRTIO_PCI_CAP_COMMON_CFG:
|
|
hw->common_cfg = get_cfg_addr(dev, &cap);
|
|
break;
|
|
case VIRTIO_PCI_CAP_NOTIFY_CFG:
|
|
rte_eal_pci_read_config(dev, &hw->notify_off_multiplier,
|
|
4, pos + sizeof(cap));
|
|
hw->notify_base = get_cfg_addr(dev, &cap);
|
|
break;
|
|
case VIRTIO_PCI_CAP_DEVICE_CFG:
|
|
hw->dev_cfg = get_cfg_addr(dev, &cap);
|
|
break;
|
|
case VIRTIO_PCI_CAP_ISR_CFG:
|
|
hw->isr = get_cfg_addr(dev, &cap);
|
|
break;
|
|
}
|
|
|
|
next:
|
|
pos = cap.cap_next;
|
|
}
|
|
|
|
if (hw->common_cfg == NULL || hw->notify_base == NULL ||
|
|
hw->dev_cfg == NULL || hw->isr == NULL) {
|
|
PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
|
|
return -1;
|
|
}
|
|
|
|
PMD_INIT_LOG(INFO, "found modern virtio pci device.");
|
|
|
|
PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
|
|
PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
|
|
PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
|
|
PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
|
|
hw->notify_base, hw->notify_off_multiplier);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Return -1:
|
|
* if there is error mapping with VFIO/UIO.
|
|
* if port map error when driver type is KDRV_NONE.
|
|
* Return 1 if kernel driver is managing the device.
|
|
* Return 0 on success.
|
|
*/
|
|
int
|
|
vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw)
|
|
{
|
|
hw->dev = dev;
|
|
|
|
/*
|
|
* Try if we can succeed reading virtio pci caps, which exists
|
|
* only on modern pci device. If failed, we fallback to legacy
|
|
* virtio handling.
|
|
*/
|
|
if (virtio_read_caps(dev, hw) == 0) {
|
|
PMD_INIT_LOG(INFO, "modern virtio pci detected.");
|
|
hw->vtpci_ops = &modern_ops;
|
|
hw->modern = 1;
|
|
dev->driver->drv_flags |= RTE_PCI_DRV_INTR_LSC;
|
|
return 0;
|
|
}
|
|
|
|
PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
|
|
if (legacy_virtio_resource_init(dev, hw) < 0) {
|
|
if (dev->kdrv == RTE_KDRV_UNKNOWN &&
|
|
dev->devargs->type != RTE_DEVTYPE_WHITELISTED_PCI) {
|
|
PMD_INIT_LOG(INFO,
|
|
"skip kernel managed virtio device.");
|
|
return 1;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
hw->vtpci_ops = &legacy_ops;
|
|
hw->use_msix = legacy_virtio_has_msix(&dev->addr);
|
|
hw->modern = 0;
|
|
|
|
return 0;
|
|
}
|