034c328eb0
Add in the list of registers for the device. And enable NTB device ops for Intel Skylake platform. Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
87 lines
3.0 KiB
C
87 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation.
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*/
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#ifndef _NTB_HW_INTEL_H_
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#define _NTB_HW_INTEL_H_
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/* Ntb control and link status */
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#define NTB_CTL_CFG_LOCK 1
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#define NTB_CTL_DISABLE 2
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#define NTB_CTL_S2P_BAR2_SNOOP (1 << 2)
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#define NTB_CTL_P2S_BAR2_SNOOP (1 << 4)
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#define NTB_CTL_S2P_BAR4_SNOOP (1 << 6)
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#define NTB_CTL_P2S_BAR4_SNOOP (1 << 8)
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#define NTB_CTL_S2P_BAR5_SNOOP (1 << 12)
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#define NTB_CTL_P2S_BAR5_SNOOP (1 << 14)
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#define NTB_LNK_STA_ACTIVE_BIT 0x2000
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#define NTB_LNK_STA_SPEED_MASK 0x000f
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#define NTB_LNK_STA_WIDTH_MASK 0x03f0
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
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/* Intel Skylake Xeon hardware */
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#define XEON_IMBAR1SZ_OFFSET 0x00d0
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#define XEON_IMBAR2SZ_OFFSET 0x00d1
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#define XEON_EMBAR1SZ_OFFSET 0x00d2
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#define XEON_EMBAR2SZ_OFFSET 0x00d3
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#define XEON_DEVCTRL_OFFSET 0x0098
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#define XEON_DEVSTS_OFFSET 0x009a
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_NTBCNTL_OFFSET 0x0000
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#define XEON_BAR_INTERVAL_OFFSET 0x0010
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#define XEON_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
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#define XEON_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
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#define XEON_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
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#define XEON_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
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#define XEON_IM_INT_STATUS_OFFSET 0x0040
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#define XEON_IM_INT_DISABLE_OFFSET 0x0048
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#define XEON_IM_SPAD_OFFSET 0x0080 /* SPAD */
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#define XEON_USMEMMISS_OFFSET 0x0070
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#define XEON_INTVEC_OFFSET 0x00d0
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#define XEON_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
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#define XEON_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
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#define XEON_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
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#define XEON_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
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#define XEON_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
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#define XEON_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
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#define XEON_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
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#define XEON_EM_INT_STATUS_OFFSET 0x4040
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#define XEON_EM_INT_DISABLE_OFFSET 0x4048
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#define XEON_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
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#define XEON_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
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#define XEON_SPCICMD_OFFSET 0x4504 /* SPCICMD */
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#define XEON_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
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#define XEON_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
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#define XEON_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
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#define XEON_PPD_OFFSET 0x00d4
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#define XEON_PPD_CONN_MASK 0x03
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#define XEON_PPD_CONN_TRANSPARENT 0x00
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#define XEON_PPD_CONN_B2B 0x01
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#define XEON_PPD_CONN_RP 0x02
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#define XEON_PPD_DEV_MASK 0x10
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#define XEON_PPD_DEV_USD 0x00
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#define XEON_PPD_DEV_DSD 0x10
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#define XEON_PPD_SPLIT_BAR_MASK 0x40
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#define XEON_MW_COUNT 2
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#define XEON_DB_COUNT 32
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#define XEON_DB_LINK 32
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#define XEON_DB_LINK_BIT (1ULL << XEON_DB_LINK)
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#define XEON_DB_MSIX_VECTOR_COUNT 33
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#define XEON_DB_MSIX_VECTOR_SHIFT 1
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#define XEON_DB_TOTAL_SHIFT 33
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#define XEON_SPAD_COUNT 16
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extern const struct ntb_dev_ops intel_ntb_ops;
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#endif /* _NTB_HW_INTEL_H_ */
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