8d3c12e193
Add API to query filter hit and byte counts from hardware. Signed-off-by: Shagun Agrawal <shaguna@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
145 lines
3.8 KiB
C
145 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Chelsio Communications.
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* All rights reserved.
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*/
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#ifndef __T4_HW_H
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#define __T4_HW_H
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enum {
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NCHAN = 4, /* # of HW channels */
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EEPROMSIZE = 17408, /* Serial EEPROM physical size */
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EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
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EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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MBOX_LEN = 64, /* mailbox size in bytes */
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UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */
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};
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enum {
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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};
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enum {
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SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
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};
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enum {
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SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
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SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
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};
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/* PCI-e memory window access */
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enum pcie_memwin {
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MEMWIN_NIC = 0,
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};
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enum {
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SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
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SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
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/* max no. of desc allowed in WR */
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SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,
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};
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enum {
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TCB_SIZE = 128, /* TCB size */
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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__be32 qid;
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__be16 cidx;
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__be16 pidx;
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};
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/*
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* Structure for last 128 bits of response descriptors
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*/
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struct rsp_ctrl {
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__be32 hdrbuflen_pidx;
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__be32 pldbuflen_qid;
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union {
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u8 type_gen;
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__be64 last_flit;
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} u;
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};
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#define S_RSPD_NEWBUF 31
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#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
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#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
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#define S_RSPD_LEN 0
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#define M_RSPD_LEN 0x7fffffff
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#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
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#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
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#define S_RSPD_GEN 7
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#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
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#define F_RSPD_GEN V_RSPD_GEN(1U)
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#define S_RSPD_TYPE 4
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#define M_RSPD_TYPE 0x3
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#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
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#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
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/* Rx queue interrupt deferral field: timer index */
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#define S_QINTR_CNT_EN 0
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#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
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#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
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#define S_QINTR_TIMER_IDX 1
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#define M_QINTR_TIMER_IDX 0x7
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#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
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#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
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/*
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* Flash layout.
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*/
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#define FLASH_START(start) ((start) * SF_SEC_SIZE)
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#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
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enum {
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/*
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* Various Expansion-ROM boot images, etc.
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*/
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FLASH_EXP_ROM_START_SEC = 0,
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FLASH_EXP_ROM_NSECS = 6,
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FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
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FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
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/*
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* Location of firmware image in FLASH.
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*/
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FLASH_FW_START_SEC = 8,
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FLASH_FW_NSECS = 16,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/*
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* Location of bootstrap firmware image in FLASH.
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*/
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FLASH_FWBOOTSTRAP_START_SEC = 27,
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FLASH_FWBOOTSTRAP_NSECS = 1,
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FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
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FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH.
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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/*
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* We don't support FLASH devices which can't support the full
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* standard set of sections which we need for normal operations.
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*/
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FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
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};
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#endif /* __T4_HW_H */
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