b8f8d1aeb2
Added registers list and structure to access the ACC200 device. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
196 lines
6.9 KiB
C
196 lines
6.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef _RTE_ACC200_PMD_H_
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#define _RTE_ACC200_PMD_H_
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#include "acc_common.h"
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#include "acc200_pf_enum.h"
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#include "acc200_vf_enum.h"
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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rte_log(RTE_LOG_ ## level, acc200_logtype, fmt "\n", \
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##__VA_ARGS__)
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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#define rte_bbdev_log_debug(fmt, ...) \
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rte_bbdev_log(DEBUG, "acc200_pmd: " fmt, \
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##__VA_ARGS__)
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#else
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#define rte_bbdev_log_debug(fmt, ...)
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#endif
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/* ACC200 PF and VF driver names */
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#define ACC200PF_DRIVER_NAME intel_acc200_pf
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#define ACC200VF_DRIVER_NAME intel_acc200_vf
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/* ACC200 PCI vendor & device IDs */
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#define RTE_ACC200_VENDOR_ID (0x8086)
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#define RTE_ACC200_PF_DEVICE_ID (0x57C0)
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#define RTE_ACC200_VF_DEVICE_ID (0x57C1)
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#define ACC200_MAX_PF_MSIX (256+32)
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#define ACC200_MAX_VF_MSIX (256+7)
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/* Values used in writing to the registers */
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#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
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/* Number of Virtual Functions ACC200 supports */
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#define ACC200_NUM_VFS 16
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#define ACC200_NUM_QGRPS 16
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#define ACC200_NUM_AQS 16
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#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
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#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
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#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
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/* Mapping of signals for the available engines */
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#define ACC200_SIG_UL_5G 0
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#define ACC200_SIG_UL_5G_LAST 4
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#define ACC200_SIG_DL_5G 10
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#define ACC200_SIG_DL_5G_LAST 11
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#define ACC200_SIG_UL_4G 12
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#define ACC200_SIG_UL_4G_LAST 16
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#define ACC200_SIG_DL_4G 21
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#define ACC200_SIG_DL_4G_LAST 23
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#define ACC200_SIG_FFT 24
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#define ACC200_SIG_FFT_LAST 24
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#define ACC200_NUM_ACCS 5
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/* ACC200 Configuration */
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#define ACC200_FABRIC_MODE 0x8000103
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#define ACC200_CFG_DMA_ERROR 0x3DF
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#define ACC200_CFG_AXI_CACHE 0x11
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#define ACC200_CFG_QMGR_HI_P 0x0F0F
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#define ACC200_RESET_HARD 0x1FF
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#define ACC200_ENGINES_MAX 9
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#define ACC200_GPEX_AXIMAP_NUM 17
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#define ACC200_CLOCK_GATING_EN 0x30000
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#define ACC200_FFT_CFG_0 0x2001
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#define ACC200_FFT_RAM_EN 0x80008000
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#define ACC200_FFT_RAM_DIS 0x0
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#define ACC200_FFT_RAM_SIZE 512
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#define ACC200_CLK_EN 0x00010A01
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#define ACC200_CLK_DIS 0x01F10A01
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#define ACC200_PG_MASK_0 0x1F
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#define ACC200_PG_MASK_1 0xF
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#define ACC200_PG_MASK_2 0x1
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#define ACC200_PG_MASK_3 0x0
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#define ACC200_PG_MASK_FFT 1
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#define ACC200_PG_MASK_4GUL 4
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#define ACC200_PG_MASK_5GUL 8
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#define ACC200_STATUS_WAIT 10
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#define ACC200_STATUS_TO 100
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struct acc200_registry_addr {
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unsigned int dma_ring_dl5g_hi;
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unsigned int dma_ring_dl5g_lo;
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unsigned int dma_ring_ul5g_hi;
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unsigned int dma_ring_ul5g_lo;
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unsigned int dma_ring_dl4g_hi;
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unsigned int dma_ring_dl4g_lo;
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unsigned int dma_ring_ul4g_hi;
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unsigned int dma_ring_ul4g_lo;
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unsigned int dma_ring_fft_hi;
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unsigned int dma_ring_fft_lo;
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unsigned int ring_size;
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unsigned int info_ring_hi;
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unsigned int info_ring_lo;
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unsigned int info_ring_en;
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unsigned int info_ring_ptr;
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unsigned int tail_ptrs_dl5g_hi;
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unsigned int tail_ptrs_dl5g_lo;
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unsigned int tail_ptrs_ul5g_hi;
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unsigned int tail_ptrs_ul5g_lo;
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unsigned int tail_ptrs_dl4g_hi;
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unsigned int tail_ptrs_dl4g_lo;
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unsigned int tail_ptrs_ul4g_hi;
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unsigned int tail_ptrs_ul4g_lo;
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unsigned int tail_ptrs_fft_hi;
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unsigned int tail_ptrs_fft_lo;
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unsigned int depth_log0_offset;
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unsigned int depth_log1_offset;
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unsigned int qman_group_func;
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unsigned int hi_mode;
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unsigned int pmon_ctrl_a;
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unsigned int pmon_ctrl_b;
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unsigned int pmon_ctrl_c;
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};
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/* Structure holding registry addresses for PF */
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static const struct acc200_registry_addr pf_reg_addr = {
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.dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf,
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.ring_size = HWPfQmgrRingSizeVf,
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.info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
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.info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
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.info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
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.info_ring_ptr = HWPfHiInfoRingPointerRegPf,
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.tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf,
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.depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWPfQmgrGrpFunction0,
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.hi_mode = HWPfHiMsixVectorMapperPf,
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.pmon_ctrl_a = HWPfPermonACntrlRegVf,
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.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
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.pmon_ctrl_c = HWPfPermonCCntrlRegVf,
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};
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/* Structure holding registry addresses for VF */
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static const struct acc200_registry_addr vf_reg_addr = {
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.dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf,
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.ring_size = HWVfQmgrRingSizeVf,
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.info_ring_hi = HWVfHiInfoRingBaseHiVf,
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.info_ring_lo = HWVfHiInfoRingBaseLoVf,
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.info_ring_en = HWVfHiInfoRingIntWrEnVf,
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.info_ring_ptr = HWVfHiInfoRingPointerVf,
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.tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf,
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.depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWVfQmgrGrpFunction0Vf,
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.hi_mode = HWVfHiMsixVectorMapperVf,
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.pmon_ctrl_a = HWVfPmACntrlRegVf,
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.pmon_ctrl_b = HWVfPmBCntrlRegVf,
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.pmon_ctrl_c = HWVfPmCCntrlRegVf,
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};
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#endif /* _RTE_ACC200_PMD_H_ */
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