16a6a44761
Ensure that support for AVX2, HLE and RTM works with cpuflags. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
284 lines
11 KiB
C
284 lines
11 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <errno.h>
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#include <stdint.h>
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#include <rte_cpuflags.h>
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/*
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* This should prevent use of advanced instruction sets in this file. Otherwise
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* the check function itself could cause a crash.
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*/
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#ifdef __INTEL_COMPILER
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#pragma optimize ("", off)
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#else
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#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
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#if GCC_VERSION > 404000
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#pragma GCC optimize ("O0")
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#endif
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#endif
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/**
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* Enumeration of CPU registers
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*/
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enum cpu_register_t {
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REG_EAX = 0,
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REG_EBX,
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REG_ECX,
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REG_EDX,
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};
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/**
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* Parameters for CPUID instruction
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*/
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struct cpuid_parameters_t {
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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enum cpu_register_t return_register;
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};
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#define CPU_FLAG_NAME_MAX_LEN 64
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/**
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* Struct to hold a processor feature entry
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*/
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struct feature_entry {
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enum rte_cpu_flag_t feature; /**< feature name */
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char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
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struct cpuid_parameters_t params; /**< cpuid parameters */
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uint32_t feature_mask; /**< bitmask for feature */
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};
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#define FEAT_DEF(f) RTE_CPUFLAG_##f, #f
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/**
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* An array that holds feature entries
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*/
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static const struct feature_entry cpu_feature_table[] = {
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{FEAT_DEF(SSE3), {0x1, 0, 0, 0, REG_ECX}, 0x00000001},
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{FEAT_DEF(PCLMULQDQ), {0x1, 0, 0, 0, REG_ECX}, 0x00000002},
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{FEAT_DEF(DTES64), {0x1, 0, 0, 0, REG_ECX}, 0x00000004},
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{FEAT_DEF(MONITOR), {0x1, 0, 0, 0, REG_ECX}, 0x00000008},
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{FEAT_DEF(DS_CPL), {0x1, 0, 0, 0, REG_ECX}, 0x00000010},
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{FEAT_DEF(VMX), {0x1, 0, 0, 0, REG_ECX}, 0x00000020},
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{FEAT_DEF(SMX), {0x1, 0, 0, 0, REG_ECX}, 0x00000040},
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{FEAT_DEF(EIST), {0x1, 0, 0, 0, REG_ECX}, 0x00000080},
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{FEAT_DEF(TM2), {0x1, 0, 0, 0, REG_ECX}, 0x00000100},
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{FEAT_DEF(SSSE3), {0x1, 0, 0, 0, REG_ECX}, 0x00000200},
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{FEAT_DEF(CNXT_ID), {0x1, 0, 0, 0, REG_ECX}, 0x00000400},
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{FEAT_DEF(FMA), {0x1, 0, 0, 0, REG_ECX}, 0x00001000},
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{FEAT_DEF(CMPXCHG16B), {0x1, 0, 0, 0, REG_ECX}, 0x00002000},
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{FEAT_DEF(XTPR), {0x1, 0, 0, 0, REG_ECX}, 0x00004000},
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{FEAT_DEF(PDCM), {0x1, 0, 0, 0, REG_ECX}, 0x00008000},
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{FEAT_DEF(PCID), {0x1, 0, 0, 0, REG_ECX}, 0x00020000},
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{FEAT_DEF(DCA), {0x1, 0, 0, 0, REG_ECX}, 0x00040000},
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{FEAT_DEF(SSE4_1), {0x1, 0, 0, 0, REG_ECX}, 0x00080000},
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{FEAT_DEF(SSE4_2), {0x1, 0, 0, 0, REG_ECX}, 0x00100000},
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{FEAT_DEF(X2APIC), {0x1, 0, 0, 0, REG_ECX}, 0x00200000},
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{FEAT_DEF(MOVBE), {0x1, 0, 0, 0, REG_ECX}, 0x00400000},
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{FEAT_DEF(POPCNT), {0x1, 0, 0, 0, REG_ECX}, 0x00800000},
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{FEAT_DEF(TSC_DEADLINE), {0x1, 0, 0, 0, REG_ECX}, 0x01000000},
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{FEAT_DEF(AES), {0x1, 0, 0, 0, REG_ECX}, 0x02000000},
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{FEAT_DEF(XSAVE), {0x1, 0, 0, 0, REG_ECX}, 0x04000000},
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{FEAT_DEF(OSXSAVE), {0x1, 0, 0, 0, REG_ECX}, 0x08000000},
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{FEAT_DEF(AVX), {0x1, 0, 0, 0, REG_ECX}, 0x10000000},
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{FEAT_DEF(F16C), {0x1, 0, 0, 0, REG_ECX}, 0x20000000},
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{FEAT_DEF(RDRAND), {0x1, 0, 0, 0, REG_ECX}, 0x40000000},
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{FEAT_DEF(FPU), {0x1, 0, 0, 0, REG_EDX}, 0x00000001},
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{FEAT_DEF(VME), {0x1, 0, 0, 0, REG_EDX}, 0x00000002},
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{FEAT_DEF(DE), {0x1, 0, 0, 0, REG_EDX}, 0x00000004},
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{FEAT_DEF(PSE), {0x1, 0, 0, 0, REG_EDX}, 0x00000008},
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{FEAT_DEF(TSC), {0x1, 0, 0, 0, REG_EDX}, 0x00000010},
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{FEAT_DEF(MSR), {0x1, 0, 0, 0, REG_EDX}, 0x00000020},
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{FEAT_DEF(PAE), {0x1, 0, 0, 0, REG_EDX}, 0x00000040},
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{FEAT_DEF(MCE), {0x1, 0, 0, 0, REG_EDX}, 0x00000080},
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{FEAT_DEF(CX8), {0x1, 0, 0, 0, REG_EDX}, 0x00000100},
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{FEAT_DEF(APIC), {0x1, 0, 0, 0, REG_EDX}, 0x00000200},
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{FEAT_DEF(SEP), {0x1, 0, 0, 0, REG_EDX}, 0x00000800},
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{FEAT_DEF(MTRR), {0x1, 0, 0, 0, REG_EDX}, 0x00001000},
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{FEAT_DEF(PGE), {0x1, 0, 0, 0, REG_EDX}, 0x00002000},
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{FEAT_DEF(MCA), {0x1, 0, 0, 0, REG_EDX}, 0x00004000},
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{FEAT_DEF(CMOV), {0x1, 0, 0, 0, REG_EDX}, 0x00008000},
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{FEAT_DEF(PAT), {0x1, 0, 0, 0, REG_EDX}, 0x00010000},
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{FEAT_DEF(PSE36), {0x1, 0, 0, 0, REG_EDX}, 0x00020000},
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{FEAT_DEF(PSN), {0x1, 0, 0, 0, REG_EDX}, 0x00040000},
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{FEAT_DEF(CLFSH), {0x1, 0, 0, 0, REG_EDX}, 0x00080000},
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{FEAT_DEF(DS), {0x1, 0, 0, 0, REG_EDX}, 0x00200000},
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{FEAT_DEF(ACPI), {0x1, 0, 0, 0, REG_EDX}, 0x00400000},
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{FEAT_DEF(MMX), {0x1, 0, 0, 0, REG_EDX}, 0x00800000},
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{FEAT_DEF(FXSR), {0x1, 0, 0, 0, REG_EDX}, 0x01000000},
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{FEAT_DEF(SSE), {0x1, 0, 0, 0, REG_EDX}, 0x02000000},
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{FEAT_DEF(SSE2), {0x1, 0, 0, 0, REG_EDX}, 0x04000000},
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{FEAT_DEF(SS), {0x1, 0, 0, 0, REG_EDX}, 0x08000000},
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{FEAT_DEF(HTT), {0x1, 0, 0, 0, REG_EDX}, 0x10000000},
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{FEAT_DEF(TM), {0x1, 0, 0, 0, REG_EDX}, 0x20000000},
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{FEAT_DEF(PBE), {0x1, 0, 0, 0, REG_EDX}, 0x80000000},
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{FEAT_DEF(DIGTEMP), {0x6, 0, 0, 0, REG_EAX}, 0x00000001},
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{FEAT_DEF(TRBOBST), {0x6, 0, 0, 0, REG_EAX}, 0x00000002},
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{FEAT_DEF(ARAT), {0x6, 0, 0, 0, REG_EAX}, 0x00000004},
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{FEAT_DEF(PLN), {0x6, 0, 0, 0, REG_EAX}, 0x00000010},
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{FEAT_DEF(ECMD), {0x6, 0, 0, 0, REG_EAX}, 0x00000020},
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{FEAT_DEF(PTM), {0x6, 0, 0, 0, REG_EAX}, 0x00000040},
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{FEAT_DEF(MPERF_APERF_MSR), {0x6, 0, 0, 0, REG_ECX}, 0x00000001},
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{FEAT_DEF(ACNT2), {0x6, 0, 0, 0, REG_ECX}, 0x00000002},
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{FEAT_DEF(ENERGY_EFF), {0x6, 0, 0, 0, REG_ECX}, 0x00000008},
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{FEAT_DEF(FSGSBASE), {0x7, 0, 0, 0, REG_EBX}, 0x00000001},
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{FEAT_DEF(BMI1), {0x7, 0, 0, 0, REG_EBX}, 0x00000004},
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{FEAT_DEF(HLE), {0x7, 0, 0, 0, REG_EBX}, 0x00000010},
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{FEAT_DEF(AVX2), {0x7, 0, 0, 0, REG_EBX}, 0x00000020},
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{FEAT_DEF(SMEP), {0x7, 0, 0, 0, REG_EBX}, 0x00000040},
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{FEAT_DEF(BMI2), {0x7, 0, 0, 0, REG_EBX}, 0x00000080},
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{FEAT_DEF(ERMS), {0x7, 0, 0, 0, REG_EBX}, 0x00000100},
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{FEAT_DEF(INVPCID), {0x7, 0, 0, 0, REG_EBX}, 0x00000400},
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{FEAT_DEF(RTM), {0x7, 0, 0, 0, REG_EBX}, 0x00000800},
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{FEAT_DEF(LAHF_SAHF), {0x80000001, 0, 0, 0, REG_ECX}, 0x00000001},
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{FEAT_DEF(LZCNT), {0x80000001, 0, 0, 0, REG_ECX}, 0x00000010},
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{FEAT_DEF(SYSCALL), {0x80000001, 0, 0, 0, REG_EDX}, 0x00000800},
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{FEAT_DEF(XD), {0x80000001, 0, 0, 0, REG_EDX}, 0x00100000},
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{FEAT_DEF(1GB_PG), {0x80000001, 0, 0, 0, REG_EDX}, 0x04000000},
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{FEAT_DEF(RDTSCP), {0x80000001, 0, 0, 0, REG_EDX}, 0x08000000},
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{FEAT_DEF(EM64T), {0x80000001, 0, 0, 0, REG_EDX}, 0x20000000},
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{FEAT_DEF(INVTSC), {0x80000007, 0, 0, 0, REG_EDX}, 0x00000100},
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};
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/*
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* Execute CPUID instruction and get contents of a specific register
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*
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* This function, when compiled with GCC, will generate architecture-neutral
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* code, as per GCC manual.
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*/
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static inline int
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rte_cpu_get_features(struct cpuid_parameters_t params)
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{
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int eax, ebx, ecx, edx; /* registers */
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#ifndef __PIC__
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asm volatile ("cpuid"
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/* output */
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: "=a" (eax),
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"=b" (ebx),
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"=c" (ecx),
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"=d" (edx)
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/* input */
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: "a" (params.eax),
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"b" (params.ebx),
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"c" (params.ecx),
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"d" (params.edx));
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#else
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asm volatile (
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"mov %%ebx, %%edi\n"
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"cpuid\n"
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"xchgl %%ebx, %%edi;\n"
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: "=a" (eax),
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"=D" (ebx),
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"=c" (ecx),
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"=d" (edx)
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/* input */
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: "a" (params.eax),
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"D" (params.ebx),
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"c" (params.ecx),
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"d" (params.edx));
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#endif
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switch (params.return_register) {
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case REG_EAX:
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return eax;
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case REG_EBX:
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return ebx;
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case REG_ECX:
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return ecx;
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case REG_EDX:
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return edx;
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default:
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return 0;
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}
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}
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/*
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* Checks if a particular flag is available on current machine.
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*/
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int
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rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
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{
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int value;
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if (feature >= RTE_CPUFLAG_NUMFLAGS)
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/* Flag does not match anything in the feature tables */
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return -ENOENT;
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/* get value of the register containing the desired feature */
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value = rte_cpu_get_features(cpu_feature_table[feature].params);
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/* check if the feature is enabled */
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return (cpu_feature_table[feature].feature_mask & value) > 0;
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}
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/**
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* Checks if the machine is adequate for running the binary. If it is not, the
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* program exits with status 1.
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* The function attribute forces this function to be called before main(). But
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* with ICC, the check is generated by the compiler.
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*/
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#ifndef __INTEL_COMPILER
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void __attribute__ ((__constructor__))
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#else
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void
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#endif
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rte_cpu_check_supported(void)
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{
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/* This is generated at compile-time by the build system */
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static const enum rte_cpu_flag_t compile_time_flags[] = {
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RTE_COMPILE_TIME_CPUFLAGS
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};
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unsigned i;
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for (i = 0; i < sizeof(compile_time_flags)/sizeof(compile_time_flags[0]); i++)
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if (rte_cpu_get_flag_enabled(compile_time_flags[i]) < 1) {
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fprintf(stderr,
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"ERROR: This system does not support \"%s\".\n"
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"Please check that RTE_MACHINE is set correctly.\n",
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cpu_feature_table[compile_time_flags[i]].name);
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exit(1);
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}
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}
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