ab6bf1d77a
Add a restriction on the pad to cache line size register. Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
1211 lines
45 KiB
C
1211 lines
45 KiB
C
/*
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* Copyright (c) 2016 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.qede_pmd for copyright and licensing details.
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*/
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/*
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* Copyright (c) 2016 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.qede_pmd for copyright and licensing details.
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*/
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#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
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0
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#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
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0xfff << 0)
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#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
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12
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#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
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0xfff << 12)
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#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
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24
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#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
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0xffUL << 24) /* @DPDK */
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#define XSDM_REG_OPERATION_GEN \
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0xf80408UL
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#define NIG_REG_RX_BRB_OUT_EN \
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0x500e18UL
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#define NIG_REG_STORM_OUT_EN \
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0x500e08UL
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#define PSWRQ2_REG_L2P_VALIDATE_VFID \
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0x240c50UL
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#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
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0x2aae04UL
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#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
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0x2aa16cUL
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#define BAR0_MAP_REG_MSDM_RAM \
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0x1d00000UL
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#define BAR0_MAP_REG_USDM_RAM \
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0x1d80000UL
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#define BAR0_MAP_REG_PSDM_RAM \
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0x1f00000UL
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#define BAR0_MAP_REG_TSDM_RAM \
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0x1c80000UL
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#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
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0x5011f4UL
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#define PRS_REG_SEARCH_TCP \
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0x1f0400UL
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#define PRS_REG_SEARCH_UDP \
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0x1f0404UL
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#define PRS_REG_SEARCH_OPENFLOW \
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0x1f0434UL
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#define TM_REG_PF_ENABLE_CONN \
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0x2c043cUL
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#define TM_REG_PF_ENABLE_TASK \
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0x2c0444UL
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#define TM_REG_PF_SCAN_ACTIVE_CONN \
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0x2c04fcUL
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#define TM_REG_PF_SCAN_ACTIVE_TASK \
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0x2c0500UL
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#define IGU_REG_LEADING_EDGE_LATCH \
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0x18082cUL
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#define IGU_REG_TRAILING_EDGE_LATCH \
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0x180830UL
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#define QM_REG_USG_CNT_PF_TX \
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0x2f2eacUL
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#define QM_REG_USG_CNT_PF_OTHER \
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0x2f2eb0UL
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#define DORQ_REG_PF_DB_ENABLE \
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0x100508UL
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#define QM_REG_PF_EN \
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0x2f2ea4UL
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#define TCFC_REG_STRONG_ENABLE_PF \
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0x2d0708UL
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#define CCFC_REG_STRONG_ENABLE_PF \
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0x2e0708UL
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#define PGLUE_B_REG_PGL_ADDR_88_F0 \
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0x2aa404UL
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#define PGLUE_B_REG_PGL_ADDR_8C_F0 \
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0x2aa408UL
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#define PGLUE_B_REG_PGL_ADDR_90_F0 \
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0x2aa40cUL
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#define PGLUE_B_REG_PGL_ADDR_94_F0 \
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0x2aa410UL
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#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
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0x2aa138UL
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#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
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0x2aa174UL
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#define MISC_REG_GEN_PURP_CR0 \
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0x008c80UL
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#define MCP_REG_SCRATCH \
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0xe20000UL
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#define CNIG_REG_NW_PORT_MODE_BB_B0 \
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0x218200UL
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#define MISCS_REG_CHIP_NUM \
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0x00976cUL
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#define MISCS_REG_CHIP_REV \
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0x009770UL
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#define MISCS_REG_CMT_ENABLED_FOR_PAIR \
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0x00971cUL
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#define MISCS_REG_CHIP_TEST_REG \
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0x009778UL
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#define MISCS_REG_CHIP_METAL \
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0x009774UL
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#define BRB_REG_HEADER_SIZE \
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0x340804UL
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#define BTB_REG_HEADER_SIZE \
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0xdb0804UL
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#define CAU_REG_LONG_TIMEOUT_THRESHOLD \
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0x1c0708UL
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#define CCFC_REG_ACTIVITY_COUNTER \
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0x2e8800UL
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#define CDU_REG_CID_ADDR_PARAMS \
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0x580900UL
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#define DBG_REG_CLIENT_ENABLE \
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0x010004UL
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#define DMAE_REG_INIT \
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0x00c000UL
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#define DORQ_REG_IFEN \
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0x100040UL
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#define GRC_REG_TIMEOUT_EN \
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0x050404UL
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#define IGU_REG_BLOCK_CONFIGURATION \
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0x180040UL
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#define MCM_REG_INIT \
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0x1200000UL
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#define MCP2_REG_DBG_DWORD_ENABLE \
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0x052404UL
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#define MISC_REG_PORT_MODE \
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0x008c00UL
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#define MISC_REG_BLOCK_256B_EN \
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0x008c14UL
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#define MISCS_REG_RESET_PL_HV \
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0x009060UL
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#define MISCS_REG_CLK_100G_MODE \
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0x009070UL
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#define MISCS_REG_RESET_PL_HV_2 \
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0x009150UL
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#define MSDM_REG_ENABLE_IN1 \
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0xfc0004UL
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#define MSEM_REG_ENABLE_IN \
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0x1800004UL
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#define NIG_REG_CM_HDR \
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0x500840UL
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#define NCSI_REG_CONFIG \
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0x040200UL
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#define PSWRQ2_REG_RBC_DONE \
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0x240000UL
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#define PSWRQ2_REG_CFG_DONE \
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0x240004UL
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#define PBF_REG_INIT \
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0xd80000UL
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#define PTU_REG_ATC_INIT_ARRAY \
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0x560000UL
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#define PCM_REG_INIT \
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0x1100000UL
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#define PGLUE_B_REG_ADMIN_PER_PF_REGION \
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0x2a9000UL
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#define PRM_REG_DISABLE_PRM \
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0x230000UL
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#define PRS_REG_SOFT_RST \
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0x1f0000UL
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#define PSDM_REG_ENABLE_IN1 \
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0xfa0004UL
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#define PSEM_REG_ENABLE_IN \
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0x1600004UL
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#define PSWRQ_REG_DBG_SELECT \
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0x280020UL
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#define PSWRQ2_REG_CDUT_P_SIZE \
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0x24000cUL
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#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
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0x2a0040UL
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#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
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0x29e050UL
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#define PSWRD_REG_DBG_SELECT \
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0x29c040UL
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#define PSWRD2_REG_CONF11 \
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0x29d064UL
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#define PSWWR_REG_USDM_FULL_TH \
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0x29a040UL
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#define PSWWR2_REG_CDU_FULL_TH2 \
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0x29b040UL
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#define QM_REG_MAXPQSIZE_0 \
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0x2f0434UL
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#define RSS_REG_RSS_INIT_EN \
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0x238804UL
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#define RDIF_REG_STOP_ON_ERROR \
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0x300040UL
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#define SRC_REG_SOFT_RST \
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0x23874cUL
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#define TCFC_REG_ACTIVITY_COUNTER \
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0x2d8800UL
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#define TCM_REG_INIT \
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0x1180000UL
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#define TM_REG_PXP_READ_DATA_FIFO_INIT \
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0x2c0014UL
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#define TSDM_REG_ENABLE_IN1 \
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0xfb0004UL
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#define TSEM_REG_ENABLE_IN \
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0x1700004UL
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#define TDIF_REG_STOP_ON_ERROR \
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0x310040UL
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#define UCM_REG_INIT \
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0x1280000UL
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#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
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0x051004UL
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#define USDM_REG_ENABLE_IN1 \
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0xfd0004UL
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#define USEM_REG_ENABLE_IN \
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0x1900004UL
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#define XCM_REG_INIT \
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0x1000000UL
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#define XSDM_REG_ENABLE_IN1 \
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0xf80004UL
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#define XSEM_REG_ENABLE_IN \
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0x1400004UL
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#define YCM_REG_INIT \
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0x1080000UL
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#define YSDM_REG_ENABLE_IN1 \
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0xf90004UL
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#define YSEM_REG_ENABLE_IN \
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0x1500004UL
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#define XYLD_REG_SCBD_STRICT_PRIO \
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0x4c0000UL
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#define TMLD_REG_SCBD_STRICT_PRIO \
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0x4d0000UL
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#define MULD_REG_SCBD_STRICT_PRIO \
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0x4e0000UL
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#define YULD_REG_SCBD_STRICT_PRIO \
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0x4c8000UL
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#define MISC_REG_SHARED_MEM_ADDR \
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0x008c20UL
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#define DMAE_REG_GO_C0 \
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0x00c048UL
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#define DMAE_REG_GO_C1 \
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0x00c04cUL
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#define DMAE_REG_GO_C2 \
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0x00c050UL
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#define DMAE_REG_GO_C3 \
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0x00c054UL
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#define DMAE_REG_GO_C4 \
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0x00c058UL
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#define DMAE_REG_GO_C5 \
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0x00c05cUL
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#define DMAE_REG_GO_C6 \
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0x00c060UL
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#define DMAE_REG_GO_C7 \
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0x00c064UL
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#define DMAE_REG_GO_C8 \
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0x00c068UL
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#define DMAE_REG_GO_C9 \
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0x00c06cUL
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#define DMAE_REG_GO_C10 \
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0x00c070UL
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#define DMAE_REG_GO_C11 \
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0x00c074UL
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#define DMAE_REG_GO_C12 \
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0x00c078UL
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#define DMAE_REG_GO_C13 \
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0x00c07cUL
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#define DMAE_REG_GO_C14 \
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0x00c080UL
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#define DMAE_REG_GO_C15 \
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0x00c084UL
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#define DMAE_REG_GO_C16 \
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0x00c088UL
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#define DMAE_REG_GO_C17 \
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0x00c08cUL
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#define DMAE_REG_GO_C18 \
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0x00c090UL
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#define DMAE_REG_GO_C19 \
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0x00c094UL
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#define DMAE_REG_GO_C20 \
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0x00c098UL
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#define DMAE_REG_GO_C21 \
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0x00c09cUL
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#define DMAE_REG_GO_C22 \
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0x00c0a0UL
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#define DMAE_REG_GO_C23 \
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0x00c0a4UL
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#define DMAE_REG_GO_C24 \
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0x00c0a8UL
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#define DMAE_REG_GO_C25 \
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0x00c0acUL
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#define DMAE_REG_GO_C26 \
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0x00c0b0UL
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#define DMAE_REG_GO_C27 \
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0x00c0b4UL
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#define DMAE_REG_GO_C28 \
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0x00c0b8UL
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#define DMAE_REG_GO_C29 \
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0x00c0bcUL
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#define DMAE_REG_GO_C30 \
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0x00c0c0UL
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#define DMAE_REG_GO_C31 \
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0x00c0c4UL
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#define DMAE_REG_CMD_MEM \
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0x00c800UL
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#define QM_REG_MAXPQSIZETXSEL_0 \
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0x2f0440UL
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#define QM_REG_SDMCMDREADY \
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0x2f1e10UL
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#define QM_REG_SDMCMDADDR \
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0x2f1e04UL
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#define QM_REG_SDMCMDDATALSB \
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0x2f1e08UL
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#define QM_REG_SDMCMDDATAMSB \
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0x2f1e0cUL
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#define QM_REG_SDMCMDGO \
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0x2f1e14UL
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|
#define QM_REG_RLPFCRD \
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0x2f4d80UL
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#define QM_REG_RLPFINCVAL \
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0x2f4c80UL
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#define QM_REG_RLGLBLCRD \
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0x2f4400UL
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#define QM_REG_RLGLBLINCVAL \
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0x2f3400UL
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#define IGU_REG_ATTENTION_ENABLE \
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0x18083cUL
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#define IGU_REG_ATTN_MSG_ADDR_L \
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0x180820UL
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#define IGU_REG_ATTN_MSG_ADDR_H \
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0x180824UL
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#define MISC_REG_AEU_GENERAL_ATTN_0 \
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0x008400UL
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#define CAU_REG_SB_ADDR_MEMORY \
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0x1c8000UL
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#define CAU_REG_SB_VAR_MEMORY \
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0x1c6000UL
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#define CAU_REG_PI_MEMORY \
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0x1d0000UL
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#define IGU_REG_PF_CONFIGURATION \
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0x180800UL
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#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
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0x00849cUL
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#define MISC_REG_AEU_MASK_ATTN_IGU \
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0x008494UL
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#define IGU_REG_CLEANUP_STATUS_0 \
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0x180980UL
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#define IGU_REG_CLEANUP_STATUS_1 \
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0x180a00UL
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#define IGU_REG_CLEANUP_STATUS_2 \
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0x180a80UL
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|
#define IGU_REG_CLEANUP_STATUS_3 \
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0x180b00UL
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#define IGU_REG_CLEANUP_STATUS_4 \
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|
0x180b80UL
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|
#define IGU_REG_COMMAND_REG_32LSB_DATA \
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|
0x180840UL
|
|
#define IGU_REG_COMMAND_REG_CTRL \
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0x180848UL
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#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
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0x1 << 1)
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#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
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0x1 << 0)
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|
#define IGU_REG_MAPPING_MEMORY \
|
|
0x184000UL
|
|
#define MISCS_REG_GENERIC_POR_0 \
|
|
0x0096d4UL
|
|
#define MCP_REG_NVM_CFG4 \
|
|
0xe0642cUL
|
|
#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
|
|
0x7 << 0)
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|
#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
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0
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|
#define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL
|
|
#define CNIG_REG_PMEG_IF_CMD_BB_B0 0x21821cUL
|
|
#define CNIG_REG_PMEG_IF_ADDR_BB_B0 0x218224UL
|
|
#define CNIG_REG_PMEG_IF_WRDATA_BB_B0 0x218228UL
|
|
#define NWM_REG_MAC0 0x800400UL
|
|
#define NWM_REG_MAC0_SIZE 256
|
|
#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
|
|
#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT 0
|
|
#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT 1
|
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#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT 3
|
|
#define ETH_MAC_REG_XIF_MODE 0x000080UL
|
|
#define ETH_MAC_REG_XIF_MODE_XGMII_SHIFT 0
|
|
#define ETH_MAC_REG_FRM_LENGTH 0x000014UL
|
|
#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT 0
|
|
#define ETH_MAC_REG_TX_IPG_LENGTH 0x000044UL
|
|
#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT 0
|
|
#define ETH_MAC_REG_RX_FIFO_SECTIONS 0x00001cUL
|
|
#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT 0
|
|
#define ETH_MAC_REG_TX_FIFO_SECTIONS 0x000020UL
|
|
#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT 16
|
|
#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT 0
|
|
#define ETH_MAC_REG_COMMAND_CONFIG 0x000008UL
|
|
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL
|
|
#define MISC_REG_XMAC_CORE_PORT_MODE 0x008c08UL
|
|
#define MISC_REG_XMAC_PHY_PORT_MODE 0x008c04UL
|
|
#define XMAC_REG_MODE 0x210008UL
|
|
#define XMAC_REG_RX_MAX_SIZE 0x210040UL
|
|
#define XMAC_REG_TX_CTRL_LO 0x210020UL
|
|
#define XMAC_REG_CTRL 0x210000UL
|
|
#define XMAC_REG_RX_CTRL 0x210030UL
|
|
#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12)
|
|
#define MISC_REG_CLK_100G_MODE 0x008c10UL
|
|
#define MISC_REG_OPTE_MODE 0x008c0cUL
|
|
#define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL
|
|
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
|
|
#define PRS_REG_SEARCH_TAG1 0x1f0444UL
|
|
#define PRS_REG_SEARCH_TCP_FIRST_FRAG 0x1f0410UL
|
|
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL
|
|
#define MISCS_REG_ECO_RESERVED 0x0097b4UL
|
|
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL
|
|
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
|
|
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
|
|
#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
|
|
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
|
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#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
|
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#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
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#define NIG_REG_LLH_FUNC_FILTER_MODE 0x501ac0UL
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#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL
|
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#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
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#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
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#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
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#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
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#define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL
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#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16
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#define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL
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#define XMAC_REG_CTRL_TX_EN (0x1 << 0)
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#define XMAC_REG_CTRL_RX_EN (0x1 << 1)
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#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */
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#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16)
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#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16
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#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16)
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#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */
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#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0)
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#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0
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#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0)
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#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0
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#define PSWRQ2_REG_ILT_MEMORY 0x260000UL
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#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
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#define QM_REG_WFQVPWEIGHT 0x2fa000UL
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#define NIG_REG_LB_ARB_CREDIT_WEIGHT_0 0x50160cUL
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#define NIG_REG_TX_ARB_CREDIT_WEIGHT_0 0x501f88UL
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#define NIG_REG_LB_ARB_CREDIT_WEIGHT_1 0x501610UL
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#define NIG_REG_TX_ARB_CREDIT_WEIGHT_1 0x501f8cUL
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#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 0x5015e4UL
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#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL
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#define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 0x5015e8UL
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#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 0x501f5cUL
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#define NIG_REG_LB_ARB_CLIENT_IS_STRICT 0x5015c0UL
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#define NIG_REG_TX_ARB_CLIENT_IS_STRICT 0x501f34UL
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#define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ 0x5015c4UL
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#define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x501f38UL
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#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT 1
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#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL
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#define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD 0x501f20UL
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#define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE 0x501f24UL
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#define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE 0x501f28UL
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#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT 0
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#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT 1
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#define NIG_REG_LB_BRBRATELIMIT_CTRL 0x50150cUL
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#define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD 0x501510UL
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#define NIG_REG_LB_BRBRATELIMIT_INC_VALUE 0x501514UL
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#define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE 0x501518UL
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#define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT 0
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#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT 1
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#define NIG_REG_LB_TCRATELIMIT_CTRL_0 0x501520UL
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#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL
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#define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 0x501560UL
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#define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 0x501580UL
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#define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT 0
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#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL
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#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL
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#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 0x1f0540UL
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#define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 0x1f0534UL
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#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 0x1f053cUL
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#define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 0x1f0530UL
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|
#define PRS_REG_ETS_ARB_CLIENT_IS_STRICT 0x1f0514UL
|
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#define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ 0x1f0518UL
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|
#define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL
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|
#define BRB_REG_SHARED_HR_AREA 0x340880UL
|
|
#define BRB_REG_TC_GUARANTIED_0 0x340900UL
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#define BRB_REG_MAIN_TC_GUARANTIED_HYST_0 0x340978UL
|
|
#define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 0x340c60UL
|
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#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL
|
|
#define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 0x340ab0UL
|
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#define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 0x340b88UL
|
|
#define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 0x340c00UL
|
|
#define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 0x340cd8UL
|
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#define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 0x340a50UL
|
|
#define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 0x340b28UL
|
|
#define PRS_REG_VXLAN_PORT 0x1f0738UL
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|
#define NIG_REG_VXLAN_PORT 0x50105cUL
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|
#define PBF_REG_VXLAN_PORT 0xd80518UL
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|
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
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|
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
|
|
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
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#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
|
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#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
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#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
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|
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
|
|
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
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|
#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
|
|
#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
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#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
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|
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
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|
#define PRS_REG_NGE_PORT 0x1f086cUL
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#define NIG_REG_NGE_PORT 0x508b38UL
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|
#define PBF_REG_NGE_PORT 0xd8051cUL
|
|
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
|
|
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
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|
#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
|
|
#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
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|
#define NIG_REG_NGE_COMP_VER 0x508b30UL
|
|
#define PBF_REG_NGE_COMP_VER 0xd80524UL
|
|
#define PRS_REG_NGE_COMP_VER 0x1f0878UL
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|
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
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|
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
|
|
#define NIG_REG_PKT_PRIORITY_TO_TC 0x501ba4UL
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|
#define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL
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|
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL
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|
#define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL
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|
#define MCP_REG_CPU_STATE 0xe05004UL
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#define MCP_REG_CPU_MODE 0xe05000UL
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|
#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10)
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|
#define MCP_REG_CPU_EVENT_MASK 0xe05008UL
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|
#define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL
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|
#define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL
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|
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL
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|
#define PSWHST_REG_INCORRECT_ACCESS_VALID 0x2a0070UL
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|
#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS 0x2a0074UL
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|
#define PSWHST_REG_INCORRECT_ACCESS_DATA 0x2a0068UL
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|
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL
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|
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL
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|
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL
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|
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 0x050050UL
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|
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x2aa150UL
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|
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x2aa144UL
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|
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x2aa148UL
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|
#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x2aa14cUL
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|
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x2aa160UL
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|
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x2aa154UL
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#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x2aa158UL
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#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x2aa15cUL
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|
#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL 0x2aa164UL
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|
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL
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|
#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 0x2aa544UL
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#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 0x2aa548UL
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|
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 0x2aae80UL
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#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 0x2aae74UL
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#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL
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|
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL
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#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL
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|
#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10)
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#define DORQ_REG_DB_DROP_REASON 0x100a2cUL
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|
#define DORQ_REG_DB_DROP_DETAILS 0x100a24UL
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|
#define TM_REG_INT_STS_1 0x2c0190UL
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|
#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6)
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#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5)
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#define TM_REG_INT_MASK_1 0x2c0194UL
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|
#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5)
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|
#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6)
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|
#define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL
|
|
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL
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|
#define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL
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#define YSEM_REG_FAST_MEMORY 0x1540000UL
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|
#define NIG_REG_FLOWCTRL_MODE 0x501ba0UL
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|
#define TSEM_REG_FAST_MEMORY 0x1740000UL
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|
#define TSEM_REG_DBG_FRAME_MODE 0x1701408UL
|
|
#define TSEM_REG_SLOW_DBG_ACTIVE 0x1701400UL
|
|
#define TSEM_REG_SLOW_DBG_MODE 0x1701404UL
|
|
#define TSEM_REG_DBG_MODE1_CFG 0x1701420UL
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|
#define TSEM_REG_SYNC_DBG_EMPTY 0x1701160UL
|
|
#define TSEM_REG_SLOW_DBG_EMPTY 0x1701140UL
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|
#define TCM_REG_CTX_RBC_ACCS 0x11814c0UL
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|
#define TCM_REG_AGG_CON_CTX 0x11814c4UL
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|
#define TCM_REG_SM_CON_CTX 0x11814ccUL
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#define TCM_REG_AGG_TASK_CTX 0x11814c8UL
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#define TCM_REG_SM_TASK_CTX 0x11814d0UL
|
|
#define MSEM_REG_FAST_MEMORY 0x1840000UL
|
|
#define MSEM_REG_DBG_FRAME_MODE 0x1801408UL
|
|
#define MSEM_REG_SLOW_DBG_ACTIVE 0x1801400UL
|
|
#define MSEM_REG_SLOW_DBG_MODE 0x1801404UL
|
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#define MSEM_REG_DBG_MODE1_CFG 0x1801420UL
|
|
#define MSEM_REG_SYNC_DBG_EMPTY 0x1801160UL
|
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#define MSEM_REG_SLOW_DBG_EMPTY 0x1801140UL
|
|
#define MCM_REG_CTX_RBC_ACCS 0x1201800UL
|
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#define MCM_REG_AGG_CON_CTX 0x1201804UL
|
|
#define MCM_REG_SM_CON_CTX 0x120180cUL
|
|
#define MCM_REG_AGG_TASK_CTX 0x1201808UL
|
|
#define MCM_REG_SM_TASK_CTX 0x1201810UL
|
|
#define USEM_REG_FAST_MEMORY 0x1940000UL
|
|
#define USEM_REG_DBG_FRAME_MODE 0x1901408UL
|
|
#define USEM_REG_SLOW_DBG_ACTIVE 0x1901400UL
|
|
#define USEM_REG_SLOW_DBG_MODE 0x1901404UL
|
|
#define USEM_REG_DBG_MODE1_CFG 0x1901420UL
|
|
#define USEM_REG_SYNC_DBG_EMPTY 0x1901160UL
|
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#define USEM_REG_SLOW_DBG_EMPTY 0x1901140UL
|
|
#define UCM_REG_CTX_RBC_ACCS 0x1281700UL
|
|
#define UCM_REG_AGG_CON_CTX 0x1281704UL
|
|
#define UCM_REG_SM_CON_CTX 0x128170cUL
|
|
#define UCM_REG_AGG_TASK_CTX 0x1281708UL
|
|
#define UCM_REG_SM_TASK_CTX 0x1281710UL
|
|
#define XSEM_REG_FAST_MEMORY 0x1440000UL
|
|
#define XSEM_REG_DBG_FRAME_MODE 0x1401408UL
|
|
#define XSEM_REG_SLOW_DBG_ACTIVE 0x1401400UL
|
|
#define XSEM_REG_SLOW_DBG_MODE 0x1401404UL
|
|
#define XSEM_REG_DBG_MODE1_CFG 0x1401420UL
|
|
#define XSEM_REG_SYNC_DBG_EMPTY 0x1401160UL
|
|
#define XSEM_REG_SLOW_DBG_EMPTY 0x1401140UL
|
|
#define XCM_REG_CTX_RBC_ACCS 0x1001800UL
|
|
#define XCM_REG_AGG_CON_CTX 0x1001804UL
|
|
#define XCM_REG_SM_CON_CTX 0x1001808UL
|
|
#define YSEM_REG_DBG_FRAME_MODE 0x1501408UL
|
|
#define YSEM_REG_SLOW_DBG_ACTIVE 0x1501400UL
|
|
#define YSEM_REG_SLOW_DBG_MODE 0x1501404UL
|
|
#define YSEM_REG_DBG_MODE1_CFG 0x1501420UL
|
|
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL
|
|
#define YCM_REG_CTX_RBC_ACCS 0x1081800UL
|
|
#define YCM_REG_AGG_CON_CTX 0x1081804UL
|
|
#define YCM_REG_SM_CON_CTX 0x108180cUL
|
|
#define YCM_REG_AGG_TASK_CTX 0x1081808UL
|
|
#define YCM_REG_SM_TASK_CTX 0x1081810UL
|
|
#define PSEM_REG_FAST_MEMORY 0x1640000UL
|
|
#define PSEM_REG_DBG_FRAME_MODE 0x1601408UL
|
|
#define PSEM_REG_SLOW_DBG_ACTIVE 0x1601400UL
|
|
#define PSEM_REG_SLOW_DBG_MODE 0x1601404UL
|
|
#define PSEM_REG_DBG_MODE1_CFG 0x1601420UL
|
|
#define PSEM_REG_SYNC_DBG_EMPTY 0x1601160UL
|
|
#define PSEM_REG_SLOW_DBG_EMPTY 0x1601140UL
|
|
#define PCM_REG_CTX_RBC_ACCS 0x1101440UL
|
|
#define PCM_REG_SM_CON_CTX 0x1101444UL
|
|
#define GRC_REG_DBG_SELECT 0x0500a4UL
|
|
#define GRC_REG_DBG_DWORD_ENABLE 0x0500a8UL
|
|
#define GRC_REG_DBG_SHIFT 0x0500acUL
|
|
#define GRC_REG_DBG_FORCE_VALID 0x0500b0UL
|
|
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL
|
|
#define PGLUE_B_REG_DBG_SELECT 0x2a8400UL
|
|
#define PGLUE_B_REG_DBG_DWORD_ENABLE 0x2a8404UL
|
|
#define PGLUE_B_REG_DBG_SHIFT 0x2a8408UL
|
|
#define PGLUE_B_REG_DBG_FORCE_VALID 0x2a840cUL
|
|
#define PGLUE_B_REG_DBG_FORCE_FRAME 0x2a8410UL
|
|
#define CNIG_REG_DBG_SELECT_K2 0x218254UL
|
|
#define CNIG_REG_DBG_DWORD_ENABLE_K2 0x218258UL
|
|
#define CNIG_REG_DBG_SHIFT_K2 0x21825cUL
|
|
#define CNIG_REG_DBG_FORCE_VALID_K2 0x218260UL
|
|
#define CNIG_REG_DBG_FORCE_FRAME_K2 0x218264UL
|
|
#define NCSI_REG_DBG_SELECT 0x040474UL
|
|
#define NCSI_REG_DBG_DWORD_ENABLE 0x040478UL
|
|
#define NCSI_REG_DBG_SHIFT 0x04047cUL
|
|
#define NCSI_REG_DBG_FORCE_VALID 0x040480UL
|
|
#define NCSI_REG_DBG_FORCE_FRAME 0x040484UL
|
|
#define BMB_REG_DBG_SELECT 0x540a7cUL
|
|
#define BMB_REG_DBG_DWORD_ENABLE 0x540a80UL
|
|
#define BMB_REG_DBG_SHIFT 0x540a84UL
|
|
#define BMB_REG_DBG_FORCE_VALID 0x540a88UL
|
|
#define BMB_REG_DBG_FORCE_FRAME 0x540a8cUL
|
|
#define PCIE_REG_DBG_SELECT 0x0547e8UL
|
|
#define PHY_PCIE_REG_DBG_SELECT 0x629fe8UL
|
|
#define PCIE_REG_DBG_DWORD_ENABLE 0x0547ecUL
|
|
#define PHY_PCIE_REG_DBG_DWORD_ENABLE 0x629fecUL
|
|
#define PCIE_REG_DBG_SHIFT 0x0547f0UL
|
|
#define PHY_PCIE_REG_DBG_SHIFT 0x629ff0UL
|
|
#define PCIE_REG_DBG_FORCE_VALID 0x0547f4UL
|
|
#define PHY_PCIE_REG_DBG_FORCE_VALID 0x629ff4UL
|
|
#define PCIE_REG_DBG_FORCE_FRAME 0x0547f8UL
|
|
#define PHY_PCIE_REG_DBG_FORCE_FRAME 0x629ff8UL
|
|
#define MCP2_REG_DBG_SELECT 0x052400UL
|
|
#define MCP2_REG_DBG_SHIFT 0x052408UL
|
|
#define MCP2_REG_DBG_FORCE_VALID 0x052440UL
|
|
#define MCP2_REG_DBG_FORCE_FRAME 0x052444UL
|
|
#define PSWHST_REG_DBG_SELECT 0x2a0100UL
|
|
#define PSWHST_REG_DBG_DWORD_ENABLE 0x2a0104UL
|
|
#define PSWHST_REG_DBG_SHIFT 0x2a0108UL
|
|
#define PSWHST_REG_DBG_FORCE_VALID 0x2a010cUL
|
|
#define PSWHST_REG_DBG_FORCE_FRAME 0x2a0110UL
|
|
#define PSWHST2_REG_DBG_SELECT 0x29e058UL
|
|
#define PSWHST2_REG_DBG_DWORD_ENABLE 0x29e05cUL
|
|
#define PSWHST2_REG_DBG_SHIFT 0x29e060UL
|
|
#define PSWHST2_REG_DBG_FORCE_VALID 0x29e064UL
|
|
#define PSWHST2_REG_DBG_FORCE_FRAME 0x29e068UL
|
|
#define PSWRD_REG_DBG_DWORD_ENABLE 0x29c044UL
|
|
#define PSWRD_REG_DBG_SHIFT 0x29c048UL
|
|
#define PSWRD_REG_DBG_FORCE_VALID 0x29c04cUL
|
|
#define PSWRD_REG_DBG_FORCE_FRAME 0x29c050UL
|
|
#define PSWRD2_REG_DBG_SELECT 0x29d400UL
|
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#define PSWRD2_REG_DBG_DWORD_ENABLE 0x29d404UL
|
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#define PSWRD2_REG_DBG_SHIFT 0x29d408UL
|
|
#define PSWRD2_REG_DBG_FORCE_VALID 0x29d40cUL
|
|
#define PSWRD2_REG_DBG_FORCE_FRAME 0x29d410UL
|
|
#define PSWWR_REG_DBG_SELECT 0x29a084UL
|
|
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL
|
|
#define PSWWR_REG_DBG_SHIFT 0x29a08cUL
|
|
#define PSWWR_REG_DBG_FORCE_VALID 0x29a090UL
|
|
#define PSWWR_REG_DBG_FORCE_FRAME 0x29a094UL
|
|
#define PSWRQ_REG_DBG_DWORD_ENABLE 0x280024UL
|
|
#define PSWRQ_REG_DBG_SHIFT 0x280028UL
|
|
#define PSWRQ_REG_DBG_FORCE_VALID 0x28002cUL
|
|
#define PSWRQ_REG_DBG_FORCE_FRAME 0x280030UL
|
|
#define PSWRQ2_REG_DBG_SELECT 0x240100UL
|
|
#define PSWRQ2_REG_DBG_DWORD_ENABLE 0x240104UL
|
|
#define PSWRQ2_REG_DBG_SHIFT 0x240108UL
|
|
#define PSWRQ2_REG_DBG_FORCE_VALID 0x24010cUL
|
|
#define PSWRQ2_REG_DBG_FORCE_FRAME 0x240110UL
|
|
#define PGLCS_REG_DBG_SELECT 0x001d14UL
|
|
#define PGLCS_REG_DBG_DWORD_ENABLE 0x001d18UL
|
|
#define PGLCS_REG_DBG_SHIFT 0x001d1cUL
|
|
#define PGLCS_REG_DBG_FORCE_VALID 0x001d20UL
|
|
#define PGLCS_REG_DBG_FORCE_FRAME 0x001d24UL
|
|
#define PTU_REG_DBG_SELECT 0x560100UL
|
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#define PTU_REG_DBG_DWORD_ENABLE 0x560104UL
|
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#define PTU_REG_DBG_SHIFT 0x560108UL
|
|
#define PTU_REG_DBG_FORCE_VALID 0x56010cUL
|
|
#define PTU_REG_DBG_FORCE_FRAME 0x560110UL
|
|
#define DMAE_REG_DBG_SELECT 0x00c510UL
|
|
#define DMAE_REG_DBG_DWORD_ENABLE 0x00c514UL
|
|
#define DMAE_REG_DBG_SHIFT 0x00c518UL
|
|
#define DMAE_REG_DBG_FORCE_VALID 0x00c51cUL
|
|
#define DMAE_REG_DBG_FORCE_FRAME 0x00c520UL
|
|
#define TCM_REG_DBG_SELECT 0x1180040UL
|
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#define TCM_REG_DBG_DWORD_ENABLE 0x1180044UL
|
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#define TCM_REG_DBG_SHIFT 0x1180048UL
|
|
#define TCM_REG_DBG_FORCE_VALID 0x118004cUL
|
|
#define TCM_REG_DBG_FORCE_FRAME 0x1180050UL
|
|
#define MCM_REG_DBG_SELECT 0x1200040UL
|
|
#define MCM_REG_DBG_DWORD_ENABLE 0x1200044UL
|
|
#define MCM_REG_DBG_SHIFT 0x1200048UL
|
|
#define MCM_REG_DBG_FORCE_VALID 0x120004cUL
|
|
#define MCM_REG_DBG_FORCE_FRAME 0x1200050UL
|
|
#define UCM_REG_DBG_SELECT 0x1280050UL
|
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#define UCM_REG_DBG_DWORD_ENABLE 0x1280054UL
|
|
#define UCM_REG_DBG_SHIFT 0x1280058UL
|
|
#define UCM_REG_DBG_FORCE_VALID 0x128005cUL
|
|
#define UCM_REG_DBG_FORCE_FRAME 0x1280060UL
|
|
#define XCM_REG_DBG_SELECT 0x1000040UL
|
|
#define XCM_REG_DBG_DWORD_ENABLE 0x1000044UL
|
|
#define XCM_REG_DBG_SHIFT 0x1000048UL
|
|
#define XCM_REG_DBG_FORCE_VALID 0x100004cUL
|
|
#define XCM_REG_DBG_FORCE_FRAME 0x1000050UL
|
|
#define YCM_REG_DBG_SELECT 0x1080040UL
|
|
#define YCM_REG_DBG_DWORD_ENABLE 0x1080044UL
|
|
#define YCM_REG_DBG_SHIFT 0x1080048UL
|
|
#define YCM_REG_DBG_FORCE_VALID 0x108004cUL
|
|
#define YCM_REG_DBG_FORCE_FRAME 0x1080050UL
|
|
#define PCM_REG_DBG_SELECT 0x1100040UL
|
|
#define PCM_REG_DBG_DWORD_ENABLE 0x1100044UL
|
|
#define PCM_REG_DBG_SHIFT 0x1100048UL
|
|
#define PCM_REG_DBG_FORCE_VALID 0x110004cUL
|
|
#define PCM_REG_DBG_FORCE_FRAME 0x1100050UL
|
|
#define QM_REG_DBG_SELECT 0x2f2e74UL
|
|
#define QM_REG_DBG_DWORD_ENABLE 0x2f2e78UL
|
|
#define QM_REG_DBG_SHIFT 0x2f2e7cUL
|
|
#define QM_REG_DBG_FORCE_VALID 0x2f2e80UL
|
|
#define QM_REG_DBG_FORCE_FRAME 0x2f2e84UL
|
|
#define TM_REG_DBG_SELECT 0x2c07a8UL
|
|
#define TM_REG_DBG_DWORD_ENABLE 0x2c07acUL
|
|
#define TM_REG_DBG_SHIFT 0x2c07b0UL
|
|
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL
|
|
#define TM_REG_DBG_FORCE_FRAME 0x2c07b8UL
|
|
#define DORQ_REG_DBG_SELECT 0x100ad0UL
|
|
#define DORQ_REG_DBG_DWORD_ENABLE 0x100ad4UL
|
|
#define DORQ_REG_DBG_SHIFT 0x100ad8UL
|
|
#define DORQ_REG_DBG_FORCE_VALID 0x100adcUL
|
|
#define DORQ_REG_DBG_FORCE_FRAME 0x100ae0UL
|
|
#define BRB_REG_DBG_SELECT 0x340ed0UL
|
|
#define BRB_REG_DBG_DWORD_ENABLE 0x340ed4UL
|
|
#define BRB_REG_DBG_SHIFT 0x340ed8UL
|
|
#define BRB_REG_DBG_FORCE_VALID 0x340edcUL
|
|
#define BRB_REG_DBG_FORCE_FRAME 0x340ee0UL
|
|
#define SRC_REG_DBG_SELECT 0x238700UL
|
|
#define SRC_REG_DBG_DWORD_ENABLE 0x238704UL
|
|
#define SRC_REG_DBG_SHIFT 0x238708UL
|
|
#define SRC_REG_DBG_FORCE_VALID 0x23870cUL
|
|
#define SRC_REG_DBG_FORCE_FRAME 0x238710UL
|
|
#define PRS_REG_DBG_SELECT 0x1f0b6cUL
|
|
#define PRS_REG_DBG_DWORD_ENABLE 0x1f0b70UL
|
|
#define PRS_REG_DBG_SHIFT 0x1f0b74UL
|
|
#define PRS_REG_DBG_FORCE_VALID 0x1f0ba0UL
|
|
#define PRS_REG_DBG_FORCE_FRAME 0x1f0ba4UL
|
|
#define TSDM_REG_DBG_SELECT 0xfb0e28UL
|
|
#define TSDM_REG_DBG_DWORD_ENABLE 0xfb0e2cUL
|
|
#define TSDM_REG_DBG_SHIFT 0xfb0e30UL
|
|
#define TSDM_REG_DBG_FORCE_VALID 0xfb0e34UL
|
|
#define TSDM_REG_DBG_FORCE_FRAME 0xfb0e38UL
|
|
#define MSDM_REG_DBG_SELECT 0xfc0e28UL
|
|
#define MSDM_REG_DBG_DWORD_ENABLE 0xfc0e2cUL
|
|
#define MSDM_REG_DBG_SHIFT 0xfc0e30UL
|
|
#define MSDM_REG_DBG_FORCE_VALID 0xfc0e34UL
|
|
#define MSDM_REG_DBG_FORCE_FRAME 0xfc0e38UL
|
|
#define USDM_REG_DBG_SELECT 0xfd0e28UL
|
|
#define USDM_REG_DBG_DWORD_ENABLE 0xfd0e2cUL
|
|
#define USDM_REG_DBG_SHIFT 0xfd0e30UL
|
|
#define USDM_REG_DBG_FORCE_VALID 0xfd0e34UL
|
|
#define USDM_REG_DBG_FORCE_FRAME 0xfd0e38UL
|
|
#define XSDM_REG_DBG_SELECT 0xf80e28UL
|
|
#define XSDM_REG_DBG_DWORD_ENABLE 0xf80e2cUL
|
|
#define XSDM_REG_DBG_SHIFT 0xf80e30UL
|
|
#define XSDM_REG_DBG_FORCE_VALID 0xf80e34UL
|
|
#define XSDM_REG_DBG_FORCE_FRAME 0xf80e38UL
|
|
#define YSDM_REG_DBG_SELECT 0xf90e28UL
|
|
#define YSDM_REG_DBG_DWORD_ENABLE 0xf90e2cUL
|
|
#define YSDM_REG_DBG_SHIFT 0xf90e30UL
|
|
#define YSDM_REG_DBG_FORCE_VALID 0xf90e34UL
|
|
#define YSDM_REG_DBG_FORCE_FRAME 0xf90e38UL
|
|
#define PSDM_REG_DBG_SELECT 0xfa0e28UL
|
|
#define PSDM_REG_DBG_DWORD_ENABLE 0xfa0e2cUL
|
|
#define PSDM_REG_DBG_SHIFT 0xfa0e30UL
|
|
#define PSDM_REG_DBG_FORCE_VALID 0xfa0e34UL
|
|
#define PSDM_REG_DBG_FORCE_FRAME 0xfa0e38UL
|
|
#define TSEM_REG_DBG_SELECT 0x1701528UL
|
|
#define TSEM_REG_DBG_DWORD_ENABLE 0x170152cUL
|
|
#define TSEM_REG_DBG_SHIFT 0x1701530UL
|
|
#define TSEM_REG_DBG_FORCE_VALID 0x1701534UL
|
|
#define TSEM_REG_DBG_FORCE_FRAME 0x1701538UL
|
|
#define MSEM_REG_DBG_SELECT 0x1801528UL
|
|
#define MSEM_REG_DBG_DWORD_ENABLE 0x180152cUL
|
|
#define MSEM_REG_DBG_SHIFT 0x1801530UL
|
|
#define MSEM_REG_DBG_FORCE_VALID 0x1801534UL
|
|
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL
|
|
#define USEM_REG_DBG_SELECT 0x1901528UL
|
|
#define USEM_REG_DBG_DWORD_ENABLE 0x190152cUL
|
|
#define USEM_REG_DBG_SHIFT 0x1901530UL
|
|
#define USEM_REG_DBG_FORCE_VALID 0x1901534UL
|
|
#define USEM_REG_DBG_FORCE_FRAME 0x1901538UL
|
|
#define XSEM_REG_DBG_SELECT 0x1401528UL
|
|
#define XSEM_REG_DBG_DWORD_ENABLE 0x140152cUL
|
|
#define XSEM_REG_DBG_SHIFT 0x1401530UL
|
|
#define XSEM_REG_DBG_FORCE_VALID 0x1401534UL
|
|
#define XSEM_REG_DBG_FORCE_FRAME 0x1401538UL
|
|
#define YSEM_REG_DBG_SELECT 0x1501528UL
|
|
#define YSEM_REG_DBG_DWORD_ENABLE 0x150152cUL
|
|
#define YSEM_REG_DBG_SHIFT 0x1501530UL
|
|
#define YSEM_REG_DBG_FORCE_VALID 0x1501534UL
|
|
#define YSEM_REG_DBG_FORCE_FRAME 0x1501538UL
|
|
#define PSEM_REG_DBG_SELECT 0x1601528UL
|
|
#define PSEM_REG_DBG_DWORD_ENABLE 0x160152cUL
|
|
#define PSEM_REG_DBG_SHIFT 0x1601530UL
|
|
#define PSEM_REG_DBG_FORCE_VALID 0x1601534UL
|
|
#define PSEM_REG_DBG_FORCE_FRAME 0x1601538UL
|
|
#define RSS_REG_DBG_SELECT 0x238c4cUL
|
|
#define RSS_REG_DBG_DWORD_ENABLE 0x238c50UL
|
|
#define RSS_REG_DBG_SHIFT 0x238c54UL
|
|
#define RSS_REG_DBG_FORCE_VALID 0x238c58UL
|
|
#define RSS_REG_DBG_FORCE_FRAME 0x238c5cUL
|
|
#define TMLD_REG_DBG_SELECT 0x4d1600UL
|
|
#define TMLD_REG_DBG_DWORD_ENABLE 0x4d1604UL
|
|
#define TMLD_REG_DBG_SHIFT 0x4d1608UL
|
|
#define TMLD_REG_DBG_FORCE_VALID 0x4d160cUL
|
|
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL
|
|
#define MULD_REG_DBG_SELECT 0x4e1600UL
|
|
#define MULD_REG_DBG_DWORD_ENABLE 0x4e1604UL
|
|
#define MULD_REG_DBG_SHIFT 0x4e1608UL
|
|
#define MULD_REG_DBG_FORCE_VALID 0x4e160cUL
|
|
#define MULD_REG_DBG_FORCE_FRAME 0x4e1610UL
|
|
#define YULD_REG_DBG_SELECT 0x4c9600UL
|
|
#define YULD_REG_DBG_DWORD_ENABLE 0x4c9604UL
|
|
#define YULD_REG_DBG_SHIFT 0x4c9608UL
|
|
#define YULD_REG_DBG_FORCE_VALID 0x4c960cUL
|
|
#define YULD_REG_DBG_FORCE_FRAME 0x4c9610UL
|
|
#define XYLD_REG_DBG_SELECT 0x4c1600UL
|
|
#define XYLD_REG_DBG_DWORD_ENABLE 0x4c1604UL
|
|
#define XYLD_REG_DBG_SHIFT 0x4c1608UL
|
|
#define XYLD_REG_DBG_FORCE_VALID 0x4c160cUL
|
|
#define XYLD_REG_DBG_FORCE_FRAME 0x4c1610UL
|
|
#define PRM_REG_DBG_SELECT 0x2306a8UL
|
|
#define PRM_REG_DBG_DWORD_ENABLE 0x2306acUL
|
|
#define PRM_REG_DBG_SHIFT 0x2306b0UL
|
|
#define PRM_REG_DBG_FORCE_VALID 0x2306b4UL
|
|
#define PRM_REG_DBG_FORCE_FRAME 0x2306b8UL
|
|
#define PBF_PB1_REG_DBG_SELECT 0xda0728UL
|
|
#define PBF_PB1_REG_DBG_DWORD_ENABLE 0xda072cUL
|
|
#define PBF_PB1_REG_DBG_SHIFT 0xda0730UL
|
|
#define PBF_PB1_REG_DBG_FORCE_VALID 0xda0734UL
|
|
#define PBF_PB1_REG_DBG_FORCE_FRAME 0xda0738UL
|
|
#define PBF_PB2_REG_DBG_SELECT 0xda4728UL
|
|
#define PBF_PB2_REG_DBG_DWORD_ENABLE 0xda472cUL
|
|
#define PBF_PB2_REG_DBG_SHIFT 0xda4730UL
|
|
#define PBF_PB2_REG_DBG_FORCE_VALID 0xda4734UL
|
|
#define PBF_PB2_REG_DBG_FORCE_FRAME 0xda4738UL
|
|
#define RPB_REG_DBG_SELECT 0x23c728UL
|
|
#define RPB_REG_DBG_DWORD_ENABLE 0x23c72cUL
|
|
#define RPB_REG_DBG_SHIFT 0x23c730UL
|
|
#define RPB_REG_DBG_FORCE_VALID 0x23c734UL
|
|
#define RPB_REG_DBG_FORCE_FRAME 0x23c738UL
|
|
#define BTB_REG_DBG_SELECT 0xdb08c8UL
|
|
#define BTB_REG_DBG_DWORD_ENABLE 0xdb08ccUL
|
|
#define BTB_REG_DBG_SHIFT 0xdb08d0UL
|
|
#define BTB_REG_DBG_FORCE_VALID 0xdb08d4UL
|
|
#define BTB_REG_DBG_FORCE_FRAME 0xdb08d8UL
|
|
#define PBF_REG_DBG_SELECT 0xd80060UL
|
|
#define PBF_REG_DBG_DWORD_ENABLE 0xd80064UL
|
|
#define PBF_REG_DBG_SHIFT 0xd80068UL
|
|
#define PBF_REG_DBG_FORCE_VALID 0xd8006cUL
|
|
#define PBF_REG_DBG_FORCE_FRAME 0xd80070UL
|
|
#define RDIF_REG_DBG_SELECT 0x300500UL
|
|
#define RDIF_REG_DBG_DWORD_ENABLE 0x300504UL
|
|
#define RDIF_REG_DBG_SHIFT 0x300508UL
|
|
#define RDIF_REG_DBG_FORCE_VALID 0x30050cUL
|
|
#define RDIF_REG_DBG_FORCE_FRAME 0x300510UL
|
|
#define TDIF_REG_DBG_SELECT 0x310500UL
|
|
#define TDIF_REG_DBG_DWORD_ENABLE 0x310504UL
|
|
#define TDIF_REG_DBG_SHIFT 0x310508UL
|
|
#define TDIF_REG_DBG_FORCE_VALID 0x31050cUL
|
|
#define TDIF_REG_DBG_FORCE_FRAME 0x310510UL
|
|
#define CDU_REG_DBG_SELECT 0x580704UL
|
|
#define CDU_REG_DBG_DWORD_ENABLE 0x580708UL
|
|
#define CDU_REG_DBG_SHIFT 0x58070cUL
|
|
#define CDU_REG_DBG_FORCE_VALID 0x580710UL
|
|
#define CDU_REG_DBG_FORCE_FRAME 0x580714UL
|
|
#define CCFC_REG_DBG_SELECT 0x2e0500UL
|
|
#define CCFC_REG_DBG_DWORD_ENABLE 0x2e0504UL
|
|
#define CCFC_REG_DBG_SHIFT 0x2e0508UL
|
|
#define CCFC_REG_DBG_FORCE_VALID 0x2e050cUL
|
|
#define CCFC_REG_DBG_FORCE_FRAME 0x2e0510UL
|
|
#define TCFC_REG_DBG_SELECT 0x2d0500UL
|
|
#define TCFC_REG_DBG_DWORD_ENABLE 0x2d0504UL
|
|
#define TCFC_REG_DBG_SHIFT 0x2d0508UL
|
|
#define TCFC_REG_DBG_FORCE_VALID 0x2d050cUL
|
|
#define TCFC_REG_DBG_FORCE_FRAME 0x2d0510UL
|
|
#define IGU_REG_DBG_SELECT 0x181578UL
|
|
#define IGU_REG_DBG_DWORD_ENABLE 0x18157cUL
|
|
#define IGU_REG_DBG_SHIFT 0x181580UL
|
|
#define IGU_REG_DBG_FORCE_VALID 0x181584UL
|
|
#define IGU_REG_DBG_FORCE_FRAME 0x181588UL
|
|
#define CAU_REG_DBG_SELECT 0x1c0ea8UL
|
|
#define CAU_REG_DBG_DWORD_ENABLE 0x1c0eacUL
|
|
#define CAU_REG_DBG_SHIFT 0x1c0eb0UL
|
|
#define CAU_REG_DBG_FORCE_VALID 0x1c0eb4UL
|
|
#define CAU_REG_DBG_FORCE_FRAME 0x1c0eb8UL
|
|
#define UMAC_REG_DBG_SELECT 0x051094UL
|
|
#define UMAC_REG_DBG_DWORD_ENABLE 0x051098UL
|
|
#define UMAC_REG_DBG_SHIFT 0x05109cUL
|
|
#define UMAC_REG_DBG_FORCE_VALID 0x0510a0UL
|
|
#define UMAC_REG_DBG_FORCE_FRAME 0x0510a4UL
|
|
#define NIG_REG_DBG_SELECT 0x502140UL
|
|
#define NIG_REG_DBG_DWORD_ENABLE 0x502144UL
|
|
#define NIG_REG_DBG_SHIFT 0x502148UL
|
|
#define NIG_REG_DBG_FORCE_VALID 0x50214cUL
|
|
#define NIG_REG_DBG_FORCE_FRAME 0x502150UL
|
|
#define WOL_REG_DBG_SELECT 0x600140UL
|
|
#define WOL_REG_DBG_DWORD_ENABLE 0x600144UL
|
|
#define WOL_REG_DBG_SHIFT 0x600148UL
|
|
#define WOL_REG_DBG_FORCE_VALID 0x60014cUL
|
|
#define WOL_REG_DBG_FORCE_FRAME 0x600150UL
|
|
#define BMBN_REG_DBG_SELECT 0x610140UL
|
|
#define BMBN_REG_DBG_DWORD_ENABLE 0x610144UL
|
|
#define BMBN_REG_DBG_SHIFT 0x610148UL
|
|
#define BMBN_REG_DBG_FORCE_VALID 0x61014cUL
|
|
#define BMBN_REG_DBG_FORCE_FRAME 0x610150UL
|
|
#define NWM_REG_DBG_SELECT 0x8000ecUL
|
|
#define NWM_REG_DBG_DWORD_ENABLE 0x8000f0UL
|
|
#define NWM_REG_DBG_SHIFT 0x8000f4UL
|
|
#define NWM_REG_DBG_FORCE_VALID 0x8000f8UL
|
|
#define NWM_REG_DBG_FORCE_FRAME 0x8000fcUL
|
|
#define BRB_REG_BIG_RAM_ADDRESS 0x340800UL
|
|
#define BRB_REG_BIG_RAM_DATA 0x341500UL
|
|
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL
|
|
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL
|
|
#define BMB_REG_BIG_RAM_ADDRESS 0x540800UL
|
|
#define BMB_REG_BIG_RAM_DATA 0x540f00UL
|
|
#define MISCS_REG_RESET_PL_UA 0x009050UL
|
|
#define MISC_REG_RESET_PL_UA 0x008050UL
|
|
#define MISC_REG_RESET_PL_HV 0x008060UL
|
|
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL
|
|
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL
|
|
#define SEM_FAST_REG_INT_RAM 0x020000UL
|
|
#define DBG_REG_DBG_BLOCK_ON 0x010454UL
|
|
#define DBG_REG_FRAMING_MODE 0x010058UL
|
|
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL
|
|
#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
|
|
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
|
|
#define SEM_FAST_REG_FILTER_CID 0x000754UL
|
|
#define SEM_FAST_REG_EVENT_ID_RANGE_STRT 0x000760UL
|
|
#define SEM_FAST_REG_EVENT_ID_RANGE_END 0x000764UL
|
|
#define SEM_FAST_REG_FILTER_EVENT_ID 0x000758UL
|
|
#define SEM_FAST_REG_EVENT_ID_MASK 0x00075cUL
|
|
#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
|
|
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL
|
|
#define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL
|
|
#define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL
|
|
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
|
|
#define DBG_REG_FILTER_ENABLE 0x0109d0UL
|
|
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
|
|
#define DBG_REG_FILTER_CNSTR_OPRTN_0 0x010a28UL
|
|
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0 0x01071cUL
|
|
#define DBG_REG_FILTER_CNSTR_DATA_0 0x0109d8UL
|
|
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0 0x01059cUL
|
|
#define DBG_REG_FILTER_CNSTR_DATA_MASK_0 0x0109f8UL
|
|
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0 0x01065cUL
|
|
#define DBG_REG_FILTER_CNSTR_FRAME_0 0x0109e8UL
|
|
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0x0105fcUL
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#define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0x010a08UL
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#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL
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#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL
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#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL
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#define DBG_REG_FILTER_CNSTR_RANGE_0 0x010a38UL
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#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL
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#define DBG_REG_FILTER_CNSTR_CYCLIC_0 0x010a68UL
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#define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0x0108fcUL
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#define DBG_REG_FILTER_CNSTR_MUST_0 0x010a48UL
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#define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0x01083cUL
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#define DBG_REG_INTR_BUFFER 0x014000UL
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#define DBG_REG_INTR_BUFFER_WR_PTR 0x010404UL
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#define DBG_REG_WRAP_ON_INT_BUFFER 0x010418UL
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#define DBG_REG_INTR_BUFFER_RD_PTR 0x010400UL
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#define DBG_REG_EXT_BUFFER_WR_PTR 0x010410UL
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#define DBG_REG_WRAP_ON_EXT_BUFFER 0x01041cUL
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#define SEM_FAST_REG_STALL_0 0x000488UL
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#define SEM_FAST_REG_STALLED 0x000494UL
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#define SEM_FAST_REG_STORM_REG_FILE 0x008000UL
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#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
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#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
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#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
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#define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL
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#define SEM_FAST_REG_VFC_ADDR 0x000b44UL
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#define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL
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#define RSS_REG_RSS_RAM_ADDR 0x238c30UL
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#define RSS_REG_RSS_RAM_DATA 0x238c20UL
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#define MISCS_REG_BLOCK_256B_EN 0x009074UL
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#define MCP_REG_CPU_REG_FILE 0xe05200UL
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#define MCP_REG_CPU_REG_FILE_SIZE 32
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#define DBG_REG_CALENDAR_OUT_DATA 0x010480UL
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#define DBG_REG_FULL_MODE 0x010060UL
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#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB 0x010430UL
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#define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB 0x010434UL
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#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
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#define DBG_REG_PCI_EXT_BUFFER_SIZE 0x010438UL
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#define DBG_REG_PCI_FUNC_NUM 0x010a98UL
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#define DBG_REG_PCI_LOGIC_ADDR 0x010460UL
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#define DBG_REG_PCI_REQ_CREDIT 0x010440UL
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#define DBG_REG_DEBUG_TARGET 0x01005cUL
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#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
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#define DBG_REG_OUTPUT_ENABLE 0x01000cUL
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#define DBG_REG_DEBUG_TARGET 0x01005cUL
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#define DBG_REG_OTHER_ENGINE_MODE 0x010010UL
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#define NIG_REG_DEBUG_PORT 0x5020d0UL
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#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL
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#define DBG_REG_ETHERNET_HDR_7 0x010b34UL
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#define DBG_REG_ETHERNET_HDR_6 0x010b30UL
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#define DBG_REG_ETHERNET_HDR_5 0x010b2cUL
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#define DBG_REG_ETHERNET_HDR_4 0x010b28UL
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#define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL
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#define DBG_REG_NIG_DATA_LIMIT_SIZE 0x01043cUL
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#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL
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#define DBG_REG_TIMESTAMP_FRAME_EN 0x010b54UL
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#define DBG_REG_TIMESTAMP_TICK 0x010b50UL
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#define DBG_REG_FILTER_ID_NUM 0x0109d4UL
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#define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0x010a78UL
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#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL
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#define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS 0x010a90UL
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#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL
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#define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE 0x010a88UL
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#define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0x010a8cUL
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#define DBG_REG_TRIGGER_ENABLE 0x01054cUL
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#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL
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#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0x01095cUL
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#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL
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#define DBG_REG_TRIGGER_STATE_SET_COUNT_0 0x010584UL
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#define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 0x01056cUL
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#define DBG_REG_NO_GRANT_ON_FULL 0x010458UL
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#define DBG_REG_STORM_ID_NUM 0x010b14UL
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#define DBG_REG_CALENDAR_SLOT0 0x010014UL
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#define DBG_REG_HW_ID_NUM 0x010b10UL
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#define DBG_REG_FILTER_ENABLE 0x0109d0UL
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#define DBG_REG_TIMESTAMP 0x010b4cUL
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#define DBG_REG_CPU_TIMEOUT 0x010450UL
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#define DBG_REG_TRIGGER_STATUS_CUR_STATE 0x010b60UL
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#define GRC_REG_TRACE_FIFO_VALID_DATA 0x050064UL
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#define GRC_REG_TRACE_FIFO 0x050068UL
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#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x181530UL
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#define IGU_REG_ERROR_HANDLING_MEMORY 0x181520UL
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#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
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#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL
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#define GRC_REG_PROTECTION_OVERRIDE_WINDOW 0x050500UL
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#define TSEM_REG_VF_ERROR 0x1700408UL
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#define USEM_REG_VF_ERROR 0x1900408UL
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#define MSEM_REG_VF_ERROR 0x1800408UL
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#define XSEM_REG_VF_ERROR 0x1400408UL
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#define YSEM_REG_VF_ERROR 0x1500408UL
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#define PSEM_REG_VF_ERROR 0x1600408UL
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#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL
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#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT 0x180408UL
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#define IGU_REG_VF_CONFIGURATION 0x180804UL
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#define PSWHST_REG_ZONE_PERMISSION_TABLE 0x2a0800UL
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#define DORQ_REG_VF_USAGE_CNT 0x1009c4UL
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#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 0xd806ccUL
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#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 0xd806c8UL
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#define PRS_REG_MSG_CT_MAIN_0 0x1f0a24UL
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#define PRS_REG_MSG_CT_LB_0 0x1f0a28UL
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#define BRB_REG_PER_TC_COUNTERS 0x341a00UL
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/* added */
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#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
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#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
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#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
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#define MISCS_REG_FUNCTION_HIDE 0x0096f0UL
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#define PCIE_REG_PRTY_MASK 0x0547b4UL
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#define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL
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#define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL
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#define SEM_FAST_REG_INT_RAM_SIZE 20480
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#define MCP_REG_SCRATCH_SIZE 57344
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#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 24
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#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 24
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#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 16
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#define DORQ_REG_DB_DROP_DETAILS_ADDRESS 0x100a1cUL
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/* 8.10.9.0 FW */
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#define NIG_REG_VXLAN_CTRL 0x50105cUL
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#define PRS_REG_SEARCH_ROCE 0x1f040cUL
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#define PRS_REG_CM_HDR_GFT 0x1f11c8UL
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#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
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#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
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#define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL
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#define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL
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#define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL
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#define PRS_REG_SEARCH_GFT 0x1f11bcUL
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#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
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#define PRS_REG_GFT_CAM 0x1f1100UL
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#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
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#define PGLUE_B_REG_MSDM_VF_SHIFT_B 0x2aa1c4UL
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#define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL
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#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL
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#define PRS_REG_SEARCH_FCOE 0x1f0408UL
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#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL
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#define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL
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#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL
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#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL
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#define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL
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#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL
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#define IGU_REG_WRITE_DONE_PENDING 0x180900UL
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#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL
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#define PRS_REG_MSG_INFO 0x1f0a1cUL
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#define BAR0_MAP_REG_XSDM_RAM 0x1e00000UL
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/* 8.18.7.0 FW */
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#define BRB_REG_INT_MASK_10 0x3401b8UL
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#define IGU_REG_PRODUCER_MEMORY 0x182000UL
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#define IGU_REG_CONSUMER_MEM 0x183000UL
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#define CDU_REG_CCFC_CTX_VALID0 0x580400UL
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#define CDU_REG_CCFC_CTX_VALID1 0x580404UL
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#define CDU_REG_TCFC_CTX_VALID0 0x580408UL
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#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
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#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
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#define MISCS_REG_RESET_PL_HV_2_K2_E5 0x009150UL
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#define CNIG_REG_NW_PORT_MODE_BB 0x218200UL
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#define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL
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#define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL
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#define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL
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#define NWM_REG_MAC0_K2_E5 0x800400UL
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#define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL
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#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0
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#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1
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#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3
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#define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL
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#define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0
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#define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL
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#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0
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#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL
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#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0
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#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL
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#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0
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#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL
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#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16
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#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0
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#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL
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#define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL
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#define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL
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#define XMAC_REG_MODE_BB 0x210008UL
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#define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL
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#define XMAC_REG_TX_CTRL_LO_BB 0x210020UL
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#define XMAC_REG_CTRL_BB 0x210000UL
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#define XMAC_REG_CTRL_TX_EN_BB (0x1 << 0)
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#define XMAC_REG_CTRL_RX_EN_BB (0x1 << 1)
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#define XMAC_REG_RX_CTRL_BB 0x210030UL
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#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1 << 12)
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#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL
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#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL
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#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5 0x2aafa0UL
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#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5 0x2aafa4UL
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#define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL
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#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL
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#define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL
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#define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL
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#define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL
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#define PCIE_REG_PRTY_MASK_K2_E5 0x0547b4UL
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#define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL
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#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
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#define NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 0x501a00UL
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#define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL
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#define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL
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#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL
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#define PSWRQ2_REG_WR_MBS0 0x240400UL
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#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL
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