This commit introduce rte_smp_mb(), rte_smp_wmb() and rte_smp_rmb(), in order to enable memory barriers between lcores. The patch does not provide any functional change for IA, the goal is to have infrastructure for weakly ordered machines like ARM to work on DPDK. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright (C) EZchip Semiconductor Ltd. 2015.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of EZchip Semiconductor nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTE_ATOMIC_TILE_H_
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#define _RTE_ATOMIC_TILE_H_
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#ifndef RTE_FORCE_INTRINSICS
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# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "generic/rte_atomic.h"
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/**
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* General memory barrier.
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*
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* Guarantees that the LOAD and STORE operations generated before the
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* barrier occur before the LOAD and STORE operations generated after.
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* This function is architecture dependent.
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*/
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static inline void rte_mb(void)
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{
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__sync_synchronize();
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}
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/**
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* Write memory barrier.
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*
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* Guarantees that the STORE operations generated before the barrier
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* occur before the STORE operations generated after.
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* This function is architecture dependent.
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*/
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static inline void rte_wmb(void)
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{
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__sync_synchronize();
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}
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/**
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* Read memory barrier.
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*
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* Guarantees that the LOAD operations generated before the barrier
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* occur before the LOAD operations generated after.
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* This function is architecture dependent.
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*/
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static inline void rte_rmb(void)
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{
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__sync_synchronize();
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}
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#define rte_smp_mb() rte_mb()
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#define rte_smp_wmb() rte_compiler_barrier()
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#define rte_smp_rmb() rte_compiler_barrier()
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_ATOMIC_TILE_H_ */
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