numam-dpdk/drivers/common
Xiaoyu Min 4d368e1da3 net/mlx5: support flow counter action for HWS
This commit adds HW steering counter action support.
The pool mechanism is the basic data structure for the HW steering
counter.

The HW steering's counter pool is based on the rte_ring of zero-copy
variation.

There are two global rte_rings:
1. free_list:
     Store the counters indexes, which are ready for use.
2. wait_reset_list:
     Store the counters indexes, which are just freed from the user and
     need to query the hardware counter to get the reset value before
     this counter can be reused again.

The counter pool also supports cache per HW steering's queues, which are
also based on the rte_ring of zero-copy variation.

The cache can be configured in size, preload, threshold, and fetch size,
they are all exposed via device args.

The main operations of the counter pool are as follows:

 - Get one counter from the pool:
   1. The user call _get_* API.
   2. If the cache is enabled, dequeue one counter index from the local
      cache:
      2. A: if the dequeued one from the local cache is still in reset
        status (counter's query_gen_when_free is equal to pool's query
        gen):
        I. Flush all counters in the local cache back to global
           wait_reset_list.
        II. Fetch _fetch_sz_ counters into the cache from the global
            free list.
        III. Fetch one counter from the cache.
   3. If the cache is empty, fetch _fetch_sz_ counters from the global
      free list into the cache and fetch one counter from the cache.
 - Free one counter into the pool:
   1. The user calls _put_* API.
   2. Put the counter into the local cache.
   3. If the local cache is full:
      A: Write back all counters above _threshold_ into the global
         wait_reset_list.
      B: Also, write back this counter into the global wait_reset_list.

When the local cache is disabled, _get_/_put_ cache directly from/into
global list.

Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-26 13:33:39 +02:00
..
cnxk crypto/cnxk: support fixed point multiplication 2022-10-07 19:46:11 +02:00
cpt common/cpt: fix build with GCC 12 2022-06-21 20:04:49 +02:00
dpaax replace zero-length arrays with flexible ones 2022-06-07 16:44:21 +02:00
iavf common/iavf: support flow subscription 2022-09-07 20:33:26 +02:00
mlx5 net/mlx5: support flow counter action for HWS 2022-10-26 13:33:39 +02:00
mvep drivers: change indentation in build files 2021-04-21 14:04:09 +02:00
octeontx eal: remove unneeded includes from a public header 2022-09-21 15:31:03 +02:00
qat crypto/qat: support SM3 hash algorithm 2022-10-02 20:33:24 +02:00
sfc_efx common/sfc_efx/base: use avail and used terms for indexes 2022-10-04 17:22:56 +02:00
meson.build drivers: remove octeontx2 drivers 2022-01-12 15:36:32 +01:00