515e4eab2b
LS1028A does not have platform cache so any reads following a hardware write will go directly to DDR. Latency of such a read is in excess of 100 core cycles, so try to prefetch more in advance to mitigate this. How much is worth prefetching really depends on traffic conditions. With congested Rx this could go up to 4 cache lines or so. But if software keeps up with hardware and follows behind Rx PI by a cache line then it's harmful in terms of performance to cache more. We would only prefetch data that's yet to be written by ENETC, which will be evicted again anyway. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Gagandeep Singh <g.singh@nxp.com>
DPDK is a set of libraries and drivers for fast packet processing. It supports many processor architectures and both FreeBSD and Linux. The DPDK uses the Open Source BSD-3-Clause license for the core libraries and drivers. The kernel components are GPL-2.0 licensed. Please check the doc directory for release notes, API documentation, and sample application information. For questions and usage discussions, subscribe to: users@dpdk.org Report bugs and issues to the development mailing list: dev@dpdk.org