Wenzhuo Lu 5d55afe895 net/e1000/base: clear ULP configuration register on ULP exit ...

There are some client PHY Ultra Low Power (ULP) register bits that are
configured by the Manageability Engine (ME) FW.

The driver must ensure that these bits are cleared on exit from ULP.
Ordinarily the ME FW would do that, but there are cases in which the
FW is not present, and the driver must handle that.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

2017-01-17 19:36:48 +01:00

..

crypto

crypto/qat: rework request builder for performance

2016-10-26 14:58:37 +02:00

net

net/e1000/base: clear ULP configuration register on ULP exit

2017-01-17 19:36:48 +01:00

Makefile

mk: fix build dependency of drivers on pmdinfogen

2016-07-08 12:04:02 +02:00