b225073dda
Sample test to verify DMA functionality, this test covers internal transfer mode. Signed-off-by: Satha Rao <skoteshwar@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
197 lines
4.4 KiB
C
197 lines
4.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _DPI_RAWDEV_H_
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#define _DPI_RAWDEV_H_
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#include "otx2_common.h"
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#include "otx2_mempool.h"
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#define DPI_QUEUE_OPEN 0x1
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#define DPI_QUEUE_CLOSE 0x2
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/* DPI VF register offsets from VF_BAR0 */
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#define DPI_VDMA_EN (0x0)
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#define DPI_VDMA_REQQ_CTL (0x8)
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#define DPI_VDMA_DBELL (0x10)
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#define DPI_VDMA_SADDR (0x18)
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#define DPI_VDMA_COUNTS (0x20)
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#define DPI_VDMA_NADDR (0x28)
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#define DPI_VDMA_IWBUSY (0x30)
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#define DPI_VDMA_CNT (0x38)
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#define DPI_VF_INT (0x100)
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#define DPI_VF_INT_W1S (0x108)
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#define DPI_VF_INT_ENA_W1C (0x110)
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#define DPI_VF_INT_ENA_W1S (0x118)
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#define DPI_MAX_VFS 8
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#define DPI_DMA_CMD_SIZE 64
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#define DPI_CHUNK_SIZE 1024
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#define DPI_QUEUE_STOP 0x0
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#define DPI_QUEUE_START 0x1
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#define DPI_VDMA_SADDR_REQ_IDLE 63
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#define DPI_MAX_POINTER 15
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#define STRM_INC(s) ((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
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#define DPI_QFINISH_TIMEOUT (10 * 1000)
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/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
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#define DPI_XTYPE_OUTBOUND (0)
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#define DPI_XTYPE_INBOUND (1)
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#define DPI_XTYPE_INTERNAL_ONLY (2)
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#define DPI_XTYPE_EXTERNAL_ONLY (3)
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#define DPI_XTYPE_MASK 0x3
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#define DPI_HDR_PT_ZBW_CA 0x0
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#define DPI_HDR_PT_ZBW_NC 0x1
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#define DPI_HDR_PT_WQP 0x2
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#define DPI_HDR_PT_WQP_NOSTATUS 0x0
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#define DPI_HDR_PT_WQP_STATUSCA 0x1
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#define DPI_HDR_PT_WQP_STATUSNC 0x3
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#define DPI_HDR_PT_CNT 0x3
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#define DPI_HDR_PT_MASK 0x3
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#define DPI_W0_TT_MASK 0x3
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#define DPI_W0_GRP_MASK 0x3FF
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/* Set Completion data to 0xFF when request submitted,
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* upon successful request completion engine reset to completion status
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*/
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#define DPI_REQ_CDATA 0xFF
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struct dpi_vf_s {
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struct rte_pci_device *dev;
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uint8_t state;
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uint16_t vf_id;
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uint8_t domain;
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uintptr_t vf_bar0;
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uintptr_t vf_bar2;
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uint16_t pool_size_m1;
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uint16_t index;
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uint64_t *base_ptr;
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void *chunk_pool;
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struct otx2_mbox *mbox;
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};
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struct dpi_rawdev_conf_s {
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void *chunk_pool;
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};
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enum dpi_dma_queue_result_e {
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DPI_DMA_QUEUE_SUCCESS = 0,
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DPI_DMA_QUEUE_NO_MEMORY = -1,
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DPI_DMA_QUEUE_INVALID_PARAM = -2,
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};
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struct dpi_dma_req_compl_s {
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uint64_t cdata;
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void (*compl_cb)(void *dev, void *arg);
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void *cb_data;
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};
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union dpi_dma_ptr_u {
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uint64_t u[2];
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struct dpi_dma_s {
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uint64_t length:16;
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uint64_t reserved:44;
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uint64_t bed:1; /* Big-Endian */
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uint64_t alloc_l2:1;
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uint64_t full_write:1;
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uint64_t invert:1;
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uint64_t ptr;
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} s;
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};
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struct dpi_dma_buf_ptr_s {
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union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
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union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
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uint8_t rptr_cnt;
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uint8_t wptr_cnt;
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struct dpi_dma_req_compl_s *comp_ptr;
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};
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struct dpi_cring_data_s {
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struct dpi_dma_req_compl_s **compl_data;
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uint16_t max_cnt;
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uint16_t head;
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uint16_t tail;
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};
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struct dpi_dma_queue_ctx_s {
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uint16_t xtype:2;
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/* Completion pointer type */
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uint16_t pt:2;
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/* Completion updated using WQE */
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uint16_t tt:2;
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uint16_t grp:10;
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uint32_t tag;
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/* Valid only for Outbound only mode */
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uint16_t aura:12;
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uint16_t csel:1;
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uint16_t ca:1;
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uint16_t fi:1;
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uint16_t ii:1;
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uint16_t fl:1;
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uint16_t pvfe:1;
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uint16_t dealloce:1;
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uint16_t req_type:2;
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uint16_t use_lock:1;
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uint16_t deallocv;
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struct dpi_cring_data_s *c_ring;
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};
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/* DPI DMA Instruction Header Format */
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union dpi_dma_instr_hdr_u {
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uint64_t u[4];
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struct dpi_dma_instr_hdr_s_s {
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uint64_t tag:32;
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uint64_t tt:2;
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uint64_t grp:10;
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uint64_t reserved_44_47:4;
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uint64_t nfst:4;
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uint64_t reserved_52_53:2;
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uint64_t nlst:4;
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uint64_t reserved_58_63:6;
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/* Word 0 - End */
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uint64_t aura:12;
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uint64_t reserved_76_79:4;
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uint64_t deallocv:16;
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uint64_t dealloce:1;
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uint64_t pvfe:1;
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uint64_t reserved_98_99:2;
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uint64_t pt:2;
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uint64_t reserved_102_103:2;
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uint64_t fl:1;
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uint64_t ii:1;
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uint64_t fi:1;
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uint64_t ca:1;
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uint64_t csel:1;
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uint64_t reserved_109_111:3;
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uint64_t xtype:2;
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uint64_t reserved_114_119:6;
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uint64_t fport:2;
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uint64_t reserved_122_123:2;
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uint64_t lport:2;
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uint64_t reserved_126_127:2;
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/* Word 1 - End */
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uint64_t ptr:64;
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/* Word 2 - End */
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uint64_t reserved_192_255:64;
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/* Word 3 - End */
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} s;
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};
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int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura);
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int otx2_dpi_queue_close(uint16_t vf_id);
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int test_otx2_dma_rawdev(uint16_t val);
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#endif /* _DPI_RAWDEV_H_ */
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