Rahul Lakkireddy 6c2809628c net/cxgbe: improve latency for slow traffic ... TX coalescing waits for ETH_COALESCE_PKT_NUM packets to be coalesced across bursts before transmitting them. For slow traffic, such as 100 PPS, this approach increases latency since packets are received one at a time and tx coalescing has to wait for ETH_COALESCE_PKT number of packets to arrive before transmitting. To fix this: - Update rx path to use status page instead and only receive packets when either the ingress interrupt timer threshold (5 us) or the ingress interrupt packet count threshold (32 packets) fires. (i.e. whichever happens first). - If number of packets coalesced is <= number of packets sent by tx burst function, stop coalescing and transmit these packets immediately. Also added compile time option to favor throughput over latency by default. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>		2017-06-12 10:41:27 +01:00
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adapter.h	net/cxgbe: improve latency for slow traffic	2017-06-12 10:41:27 +01:00
common.h	net/cxgbe: add compressed error vector	2017-06-12 10:41:27 +01:00
t4_chip_type.h	net/cxgbe: add support to run Chelsio T6 cards	2017-06-12 10:41:26 +01:00
t4_hw.c	net/cxgbe: fix port statistics	2017-06-12 10:41:27 +01:00
t4_hw.h	net/cxgbe: update hardware info prints	2017-06-12 10:41:27 +01:00
t4_msg.h	net/cxgbe: add compressed error vector	2017-06-12 10:41:27 +01:00
t4_pci_id_tbl.h	net/cxgbe: add support to run Chelsio T6 cards	2017-06-12 10:41:26 +01:00
t4_regs_values.h	net/cxgbe: improve latency for slow traffic	2017-06-12 10:41:27 +01:00
t4_regs.h	net/cxgbe: fix port statistics	2017-06-12 10:41:27 +01:00
t4fw_interface.h	net/cxgbe: improve latency for slow traffic	2017-06-12 10:41:27 +01:00