aed044bedc
Add basic PCIe ethdev probe and remove. Signed-off-by: Nalla Pradeep <pnalla@marvell.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
180 lines
5.1 KiB
C
180 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_COMMON_H_
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#define _OTX2_COMMON_H_
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#include <rte_atomic.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_kvargs.h>
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#include <rte_memory.h>
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#include <rte_memzone.h>
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#include <rte_io.h>
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#include "hw/otx2_rvu.h"
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#include "hw/otx2_nix.h"
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#include "hw/otx2_npc.h"
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#include "hw/otx2_npa.h"
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#include "hw/otx2_sdp.h"
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#include "hw/otx2_sso.h"
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#include "hw/otx2_ssow.h"
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#include "hw/otx2_tim.h"
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#include "hw/otx2_ree.h"
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/* Alignment */
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#define OTX2_ALIGN 128
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/* Bits manipulation */
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#ifndef BIT_ULL
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#define BIT_ULL(nr) (1ULL << (nr))
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#endif
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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#ifndef BITS_PER_LONG
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#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
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#endif
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#ifndef BITS_PER_LONG_LONG
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#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
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#endif
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#ifndef GENMASK
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#define GENMASK(h, l) \
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(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#endif
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#ifndef GENMASK_ULL
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#define GENMASK_ULL(h, l) \
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(((~0ULL) - (1ULL << (l)) + 1) & \
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(~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
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#endif
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#define OTX2_NPA_LOCK_MASK "npa_lock_mask"
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/* Intra device related functions */
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struct otx2_npa_lf;
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struct otx2_idev_cfg {
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uint16_t sso_pf_func;
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uint16_t npa_pf_func;
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struct otx2_npa_lf *npa_lf;
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RTE_STD_C11
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union {
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rte_atomic16_t npa_refcnt;
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uint16_t npa_refcnt_u16;
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};
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uint64_t npa_lock_mask;
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};
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__rte_internal
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struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);
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__rte_internal
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void otx2_sso_pf_func_set(uint16_t sso_pf_func);
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__rte_internal
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uint16_t otx2_sso_pf_func_get(void);
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__rte_internal
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uint16_t otx2_npa_pf_func_get(void);
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__rte_internal
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struct otx2_npa_lf *otx2_npa_lf_obj_get(void);
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__rte_internal
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void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);
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__rte_internal
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int otx2_npa_lf_active(void *dev);
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__rte_internal
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int otx2_npa_lf_obj_ref(void);
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__rte_internal
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void otx2_parse_common_devargs(struct rte_kvargs *kvlist);
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/* Log */
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extern int otx2_logtype_base;
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extern int otx2_logtype_mbox;
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extern int otx2_logtype_npa;
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extern int otx2_logtype_nix;
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extern int otx2_logtype_sso;
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extern int otx2_logtype_npc;
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extern int otx2_logtype_tm;
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extern int otx2_logtype_tim;
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extern int otx2_logtype_dpi;
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extern int otx2_logtype_ep;
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extern int otx2_logtype_ree;
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#define otx2_err(fmt, args...) \
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RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", \
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__func__, __LINE__, ## args)
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#define otx2_info(fmt, args...) \
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RTE_LOG(INFO, PMD, fmt"\n", ## args)
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#define otx2_dbg(subsystem, fmt, args...) \
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rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \
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"[%s] %s():%u " fmt "\n", \
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#subsystem, __func__, __LINE__, ##args)
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#define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)
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#define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)
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#define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)
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#define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)
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#define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)
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#define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)
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#define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
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#define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
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#define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
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#define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
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#define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__)
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/* PCI IDs */
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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#define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
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#define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
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#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
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#define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
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#define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
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#define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
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#define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
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#define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8
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#define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
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#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */
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/* OCTEON TX2 98xx EP mode */
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#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103
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#define PCI_DEVID_OCTEONTX2_EP_RAW_VF 0xB204 /* OCTEON TX2 EP mode */
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#define PCI_DEVID_OCTEONTX2_RVU_SDP_PF 0xA0f6
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#define PCI_DEVID_OCTEONTX2_RVU_SDP_VF 0xA0f7
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#define PCI_DEVID_OCTEONTX2_RVU_REE_PF 0xA0f4
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#define PCI_DEVID_OCTEONTX2_RVU_REE_VF 0xA0f5
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/*
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* REVID for RVU PCIe devices.
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* Bits 0..1: minor pass
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* Bits 3..2: major pass
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* Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
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*/
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#define RVU_PCI_REV_MIDR_ID(rev_id) (rev_id >> 4)
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#define RVU_PCI_REV_MAJOR(rev_id) ((rev_id >> 2) & 0x3)
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#define RVU_PCI_REV_MINOR(rev_id) (rev_id & 0x3)
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#define RVU_PCI_CN96XX_MIDR_ID 0x0
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#define RVU_PCI_CNF95XX_MIDR_ID 0x1
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/* PCI Config offsets */
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#define RVU_PCI_REVISION_ID 0x08
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/* IO Access */
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#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
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#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
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#if defined(RTE_ARCH_ARM64)
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#include "otx2_io_arm64.h"
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#else
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#include "otx2_io_generic.h"
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#endif
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/* Fastpath lookup */
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#define OTX2_NIX_FASTPATH_LOOKUP_MEM "otx2_nix_fastpath_lookup_mem"
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#define OTX2_NIX_SA_TBL_START (4096*4 + 69632*2)
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#endif /* _OTX2_COMMON_H_ */
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