76d794566d
The maximum number of queues for hns3 PF and VF driver is 64 based on hns3 network engine with revision_id equals 0x21. Based on hns3 network engine with revision_id equals 0x30, the hns3 PF PMD driver can support up to 1280 queues, and hns3 VF PMD driver can support up to 128 queues. The following points need to be modified to support maximizing queue number and maintain better compatibility: 1) Maximizing the number of queues for hns3 PF and VF PMD driver In current version, VF is not supported when PF is driven by hns3 PMD driver. If maximum queue numbers allocated to PF PMD driver is less than total tqps_num allocated to this port, all remaining number of queues are mapped to VF function, which is unreasonable. So we fix that all remaining number of queues are mapped to PF function. Using RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF which comes from configuration file to limit the queue number allocated to PF device based on hns3 network engine with revision_id greater than 0x30. And PF device still keep the maximum 64 queues based on hns3 network engine with revision_id equals 0x21. Remove restriction of the macro HNS3_MAX_TQP_NUM_PER_FUNC on the maximum number of queues in hns3 VF PMD driver and use the value allocated by hns3 PF kernel netdev driver. 2) According to the queue number allocated to PF device, a variable array for Rx and Tx queue is dynamically allocated to record the statistics of Rx and Tx queues during the .dev_init ops implementation function. 3) Add an extended field in hns3_pf_res_cmd to support the case that numbers of queue are greater than 1024. 4) Use new base address of Rx or Tx queue if QUEUE_ID of Rx or Tx queue is greater than 1024. 5) Remove queue id mask and use all bits of actual queue_id as the queue_id to configure hardware. 6) Currently, 0~9 bits of qset_id in hns3_nq_to_qs_link_cmd used to record actual qset id and 10 bit as VLD bit are configured to hardware. So we also need to use 11~15 bits when actual qset_id is greater than 1024. 7) The number of queue sets based on different network engine are different. We use it to calculate group number and configure to hardware in the backpressure configuration. 8) Adding check operations for number of Rx and Tx queue user configured when mapping queue to tc Rx queue numbers under a single TC must be less than rss_size_max supported by a single TC. Rx and Tx queue numbers are allocated to every TC by average. So Rx and Tx queue numbers must be an integer multiple of 2, or redundant queues are not available. 9) We can specify which packets enter the queue with a specific queue number, when creating flow table rules by rte_flow API. Currently, driver uses 0~9 bits to record the queue_id. So it is necessary to extend one bit field to record queue_id and configure to hardware, if the queue_id is greater than 1024. Signed-off-by: Huisong Li <lihuisong@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
186 lines
4.2 KiB
C
186 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_DCB_H_
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#define _HNS3_DCB_H_
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#define HNS3_ETHER_MAX_RATE 100000
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/* MAC Pause */
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#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
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#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
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#define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
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#define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
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/* SP or DWRR */
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#define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
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#define HNS3_DCB_TX_SCHD_SP_MSK (0xFE)
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enum hns3_shap_bucket {
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HNS3_DCB_SHAP_C_BUCKET = 0,
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HNS3_DCB_SHAP_P_BUCKET,
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};
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struct hns3_priority_weight_cmd {
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uint8_t pri_id;
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uint8_t dwrr;
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uint8_t rsvd[22];
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};
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struct hns3_qs_weight_cmd {
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uint16_t qs_id;
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uint8_t dwrr;
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uint8_t rsvd[21];
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};
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struct hns3_pg_weight_cmd {
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uint8_t pg_id;
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uint8_t dwrr;
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uint8_t rsvd[22];
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};
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struct hns3_ets_tc_weight_cmd {
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uint8_t tc_weight[HNS3_MAX_TC_NUM];
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uint8_t weight_offset;
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uint8_t rsvd[15];
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};
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struct hns3_qs_to_pri_link_cmd {
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uint16_t qs_id;
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uint16_t rsvd;
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uint8_t priority;
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#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
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#define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
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#define HNS3_DCB_QS_ID_L_S 0
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#define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
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#define HNS3_DCB_QS_ID_H_S 10
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#define HNS3_DCB_QS_ID_H_EXT_S 11
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#define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
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uint8_t link_vld;
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uint8_t rsvd1[18];
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};
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struct hns3_nq_to_qs_link_cmd {
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uint16_t nq_id;
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uint16_t rsvd;
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#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
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uint16_t qset_id;
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uint8_t rsvd1[18];
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};
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#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
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#define HNS3_DCB_SHAP_IR_B_LSH 0
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#define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
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#define HNS3_DCB_SHAP_IR_U_LSH 8
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#define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
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#define HNS3_DCB_SHAP_IR_S_LSH 12
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#define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
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#define HNS3_DCB_SHAP_BS_B_LSH 16
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#define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
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#define HNS3_DCB_SHAP_BS_S_LSH 21
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struct hns3_pri_shapping_cmd {
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uint8_t pri_id;
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uint8_t rsvd[3];
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uint32_t pri_shapping_para;
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uint32_t rsvd1[4];
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};
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struct hns3_pg_shapping_cmd {
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uint8_t pg_id;
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uint8_t rsvd[3];
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uint32_t pg_shapping_para;
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uint32_t rsvd1[4];
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};
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#define HNS3_BP_GRP_NUM 32
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#define HNS3_BP_SUB_GRP_ID_S 0
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#define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
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#define HNS3_BP_GRP_ID_S 5
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#define HNS3_BP_GRP_ID_M GENMASK(9, 5)
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struct hns3_bp_to_qs_map_cmd {
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uint8_t tc_id;
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uint8_t rsvd[2];
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uint8_t qs_group_id;
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uint32_t qs_bit_map;
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uint32_t rsvd1[4];
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};
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struct hns3_pfc_en_cmd {
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uint8_t tx_rx_en_bitmap;
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uint8_t pri_en_bitmap;
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uint8_t rsvd[22];
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};
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struct hns3_port_shapping_cmd {
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uint32_t port_shapping_para;
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uint32_t rsvd[5];
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};
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struct hns3_cfg_pause_param_cmd {
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t pause_trans_gap;
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uint8_t rsvd;
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uint16_t pause_trans_time;
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uint8_t rsvd1[6];
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/* extra mac address to do double check for pause frame */
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uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
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uint16_t rsvd2;
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};
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struct hns3_pg_to_pri_link_cmd {
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uint8_t pg_id;
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uint8_t rsvd1[3];
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uint8_t pri_bit_map;
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uint8_t rsvd2[19];
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};
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enum hns3_shaper_level {
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HNS3_SHAPER_LVL_PRI = 0,
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HNS3_SHAPER_LVL_PG = 1,
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HNS3_SHAPER_LVL_PORT = 2,
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HNS3_SHAPER_LVL_QSET = 3,
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HNS3_SHAPER_LVL_CNT = 4,
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HNS3_SHAPER_LVL_VF = 0,
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HNS3_SHAPER_LVL_PF = 1,
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};
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struct hns3_shaper_parameter {
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uint32_t ir_b; /* IR_B parameter of IR shaper */
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uint32_t ir_u; /* IR_U parameter of IR shaper */
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uint32_t ir_s; /* IR_S parameter of IR shaper */
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};
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#define hns3_dcb_set_field(dest, string, val) \
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hns3_set_field((dest), \
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(HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH), val)
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#define hns3_dcb_get_field(src, string) \
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hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH))
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int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
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int hns3_dcb_configure(struct hns3_adapter *hns);
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int hns3_dcb_init(struct hns3_hw *hw);
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int hns3_dcb_init_hw(struct hns3_hw *hw);
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int hns3_dcb_info_init(struct hns3_hw *hw);
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int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
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int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
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struct rte_eth_pfc_conf *pfc_conf);
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int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
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uint16_t nb_tx_q);
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int hns3_dcb_cfg_update(struct hns3_adapter *hns);
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#endif /* _HNS3_DCB_H_ */
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