b5fcebb242
Performance improvement: use a write combining store instead of a regular mmio write to update queue tail registers. Signed-off-by: Gordon Noonan <gordon.noonan@intel.com> Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
214 lines
5.3 KiB
C
214 lines
5.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017-2021 Intel Corporation
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*/
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#ifndef _IAVF_OSDEP_H_
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#define _IAVF_OSDEP_H_
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <rte_common.h>
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#include <rte_memcpy.h>
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#include <rte_memzone.h>
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#include <rte_malloc.h>
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#include <rte_byteorder.h>
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#include <rte_cycles.h>
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#include <rte_spinlock.h>
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#include <rte_log.h>
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#include <rte_io.h>
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#ifndef __INTEL_NET_BASE_OSDEP__
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#define __INTEL_NET_BASE_OSDEP__
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#define INLINE inline
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#define STATIC static
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typedef uint8_t u8;
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typedef int8_t s8;
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typedef uint16_t u16;
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typedef int16_t s16;
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typedef uint32_t u32;
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typedef int32_t s32;
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typedef uint64_t u64;
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typedef uint64_t s64;
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#ifndef __le16
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#define __le16 uint16_t
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#endif
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#ifndef __le32
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#define __le32 uint32_t
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#endif
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#ifndef __le64
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#define __le64 uint64_t
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#endif
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#ifndef __be16
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#define __be16 uint16_t
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#endif
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#ifndef __be32
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#define __be32 uint32_t
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#endif
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#ifndef __be64
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#define __be64 uint64_t
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#endif
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/* Avoid macro redefinition warning on Windows */
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#ifdef RTE_EXEC_ENV_WINDOWS
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#ifdef min
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#undef min
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#endif
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#ifdef max
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#undef max
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#endif
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#endif
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#define min(a, b) RTE_MIN(a, b)
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#define max(a, b) RTE_MAX(a, b)
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#define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f)
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#define ARRAY_SIZE(arr) RTE_DIM(arr)
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#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
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#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
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#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
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#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
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#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
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#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
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#define CPU_TO_BE16(o) rte_cpu_to_be_16(o)
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#define CPU_TO_BE32(o) rte_cpu_to_be_32(o)
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#define CPU_TO_BE64(o) rte_cpu_to_be_64(o)
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#define NTOHS(a) rte_be_to_cpu_16(a)
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#define NTOHL(a) rte_be_to_cpu_32(a)
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#define HTONS(a) rte_cpu_to_be_16(a)
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#define HTONL(a) rte_cpu_to_be_32(a)
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static __rte_always_inline uint32_t
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readl(volatile void *addr)
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{
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return rte_le_to_cpu_32(rte_read32(addr));
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}
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static __rte_always_inline void
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writel(uint32_t value, volatile void *addr)
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{
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rte_write32(rte_cpu_to_le_32(value), addr);
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}
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static __rte_always_inline void
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writel_relaxed(uint32_t value, volatile void *addr)
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{
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rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
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}
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static __rte_always_inline uint64_t
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readq(volatile void *addr)
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{
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return rte_le_to_cpu_64(rte_read64(addr));
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}
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static __rte_always_inline void
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writeq(uint64_t value, volatile void *addr)
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{
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rte_write64(rte_cpu_to_le_64(value), addr);
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}
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#define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg))
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#define rd32(a, reg) readl((a)->hw_addr + (reg))
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#define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))
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#define rd64(a, reg) readq((a)->hw_addr + (reg))
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#endif /* __INTEL_NET_BASE_OSDEP__ */
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#define iavf_memset(a, b, c, d) memset((a), (b), (c))
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#define iavf_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
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#define iavf_usec_delay(x) rte_delay_us_sleep(x)
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#define iavf_msec_delay(x) iavf_usec_delay(1000 * (x))
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#define IAVF_PCI_REG_WRITE(reg, value) writel(value, reg)
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#define IAVF_PCI_REG_WRITE_RELAXED(reg, value) writel_relaxed(value, reg)
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#define IAVF_PCI_REG_WC_WRITE(reg, value) \
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rte_write32_wc((rte_cpu_to_le_32(value)), reg)
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#define IAVF_PCI_REG_WC_WRITE_RELAXED(reg, value) \
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rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
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#define IAVF_READ_REG(hw, reg) rd32(hw, reg)
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#define IAVF_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
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#define IAVF_WRITE_FLUSH(a) IAVF_READ_REG(a, IAVF_VFGEN_RSTAT)
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extern int iavf_common_logger;
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#define DEBUGOUT(S) rte_log(RTE_LOG_DEBUG, iavf_common_logger, S)
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#define DEBUGOUT2(S, A...) rte_log(RTE_LOG_DEBUG, iavf_common_logger, S, ##A)
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#define DEBUGFUNC(F) DEBUGOUT(F "\n")
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#define iavf_debug(h, m, s, ...) \
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do { \
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if (((m) & (h)->debug_mask)) \
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rte_log(RTE_LOG_DEBUG, iavf_common_logger, \
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"iavf %02x.%x " s, \
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(h)->bus.device, (h)->bus.func, \
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##__VA_ARGS__); \
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} while (0)
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/* memory allocation tracking */
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struct iavf_dma_mem {
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void *va;
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u64 pa;
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u32 size;
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const void *zone;
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} __rte_packed;
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struct iavf_virt_mem {
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void *va;
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u32 size;
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} __rte_packed;
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/* SW spinlock */
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struct iavf_spinlock {
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rte_spinlock_t spinlock;
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};
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#define iavf_allocate_dma_mem(h, m, unused, s, a) \
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iavf_allocate_dma_mem_d(h, m, s, a)
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#define iavf_free_dma_mem(h, m) iavf_free_dma_mem_d(h, m)
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#define iavf_allocate_virt_mem(h, m, s) iavf_allocate_virt_mem_d(h, m, s)
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#define iavf_free_virt_mem(h, m) iavf_free_virt_mem_d(h, m)
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static inline void
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iavf_init_spinlock_d(struct iavf_spinlock *sp)
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{
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rte_spinlock_init(&sp->spinlock);
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}
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static inline void
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iavf_acquire_spinlock_d(struct iavf_spinlock *sp)
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{
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rte_spinlock_lock(&sp->spinlock);
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}
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static inline void
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iavf_release_spinlock_d(struct iavf_spinlock *sp)
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{
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rte_spinlock_unlock(&sp->spinlock);
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}
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static inline void
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iavf_destroy_spinlock_d(__rte_unused struct iavf_spinlock *sp)
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{
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}
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#define iavf_init_spinlock(_sp) iavf_init_spinlock_d(_sp)
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#define iavf_acquire_spinlock(_sp) iavf_acquire_spinlock_d(_sp)
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#define iavf_release_spinlock(_sp) iavf_release_spinlock_d(_sp)
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#define iavf_destroy_spinlock(_sp) iavf_destroy_spinlock_d(_sp)
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#endif /* _IAVF_OSDEP_H_ */
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