Olivier Matz a3d6026711 ring: relax alignment constraint on ring structure ... The initial objective of commit d9f0d3a1ff ("ring: remove split cacheline build setting") was to add an empty cache line between the producer and consumer data (on platform with cache line size = 64B), preventing from having them on adjacent cache lines. Following discussion on the mailing list, it appears that this also imposes an alignment constraint that is not required. This patch removes the extra alignment constraint and adds the empty cache lines using padding fields in the structure. The size of rte_ring structure and the offset of the fields remain the same on platforms with cache line size = 64B: rte_ring = 384 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 rte_ring.cons = 256 But it has an impact on platform where cache line size is 128B: rte_ring = 384 -> 768 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 -> 256 rte_ring.cons = 256 -> 512 Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>		2018-04-18 00:24:22 +02:00
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api	eventdev: introduce event timer adapter	2018-04-16 11:04:46 +02:00
guides	ring: relax alignment constraint on ring structure	2018-04-18 00:24:22 +02:00
logo	doc: change theme of guides	2015-12-13 22:30:47 +01:00
build-sdk-meson.txt	build: support vendor specific ARM cross builds	2018-01-30 21:59:00 +01:00
build-sdk-quick.txt	doc: add tags and cscope make targets to quick help	2017-08-05 11:04:47 +02:00