b94e5c9406
This implementation is based on IBM POWER version of rte_cpuflags. We use software emulation of HW capability registers, because those are usually not directly accessible from userspace on ARM. Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com> Signed-off-by: Jan Viktorin <viktorin@rehivetech.com> Acked-by: David Marchand <david.marchand@6wind.com>
124 lines
3.5 KiB
Makefile
124 lines
3.5 KiB
Makefile
# BSD LICENSE
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#
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# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Intel Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# this makefile is called from the generic rte.vars.mk and is
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# used to set the RTE_CPUFLAG_* environment variables giving details
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# of what instruction sets the target cpu supports.
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AUTO_CPUFLAGS := $(shell $(CC) $(MACHINE_CFLAGS) -dM -E - < /dev/null)
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# adding flags to CPUFLAGS
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSE__),)
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CPUFLAGS += SSE
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSE2__),)
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CPUFLAGS += SSE2
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSE3__),)
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CPUFLAGS += SSE3
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSSE3__),)
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CPUFLAGS += SSSE3
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSE4_1__),)
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CPUFLAGS += SSE4_1
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__SSE4_2__),)
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CPUFLAGS += SSE4_2
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__AES__),)
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CPUFLAGS += AES
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__PCLMUL__),)
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CPUFLAGS += PCLMULQDQ
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__AVX__),)
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CPUFLAGS += AVX
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__RDRND__),)
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CPUFLAGS += RDRAND
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__FSGSBASE__),)
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CPUFLAGS += FSGSBASE
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__F16C__),)
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CPUFLAGS += F16C
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__AVX2__),)
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CPUFLAGS += AVX2
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endif
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# IBM Power CPU flags
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ifneq ($(filter $(AUTO_CPUFLAGS),__PPC64__),)
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CPUFLAGS += PPC64
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__PPC32__),)
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CPUFLAGS += PPC32
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__vector),)
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CPUFLAGS += ALTIVEC
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endif
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ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)
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CPUFLAGS += VSX
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endif
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# ARM flags
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ifneq ($(filter $(AUTO_CPUFLAGS),__ARM_NEON_FP),)
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CPUFLAGS += NEON
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endif
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MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))
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# To strip whitespace
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comma:= ,
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empty:=
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space:= $(empty) $(empty)
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CPUFLAGSTMP1 := $(addprefix RTE_CPUFLAG_,$(CPUFLAGS))
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CPUFLAGSTMP2 := $(subst $(space),$(comma),$(CPUFLAGSTMP1))
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MACHINE_CFLAGS += -DRTE_COMPILE_TIME_CPUFLAGS=$(CPUFLAGSTMP2)
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