numam-dpdk/drivers
Qi Zhang bc696378a9 net/ice/base: fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC.  This means that traffic classes 4-7 could not be
enabled for PFC.

Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.

Fixes: 8ea78b1696 ("net/ice/base: support L3 DSCP QoS")
Cc: stable@dpdk.org

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
..
baseband dev: hide driver object 2022-09-23 16:14:34 +02:00
bus bus/pci: fill bus specific information 2022-09-23 16:14:34 +02:00
common common/iavf: support flow subscription 2022-09-07 20:33:26 +02:00
compress dev: hide driver object 2022-09-23 16:14:34 +02:00
crypto crypto/openssl: fix HMAC output length 2022-09-27 18:20:35 +02:00
dma dev: hide driver object 2022-09-23 16:14:34 +02:00
event event/cnxk: update event vector Tx routine 2022-09-27 15:41:59 +02:00
gpu dev: hide driver object 2022-09-23 16:14:34 +02:00
mempool common/cnxk: reserve AURA zero on CN10KA NPA 2022-09-22 10:44:04 +02:00
net net/ice/base: fix DSCP PFC TLV creation 2022-09-18 16:12:32 +02:00
raw raw/ioat: remove deprecated driver 2022-09-28 14:41:07 +02:00
regex dev: hide driver object 2022-09-23 16:14:34 +02:00
vdpa bus/pci: make driver-only headers private 2022-09-23 16:14:34 +02:00
meson.build build: export drivers headers 2022-09-23 16:14:34 +02:00