Rahul Lakkireddy edd04c6196 net/cxgbe: update Rx path for Chelsio T6 ... Update RX path to reflect Chelsio T6 register value changes. Update ingress pack boundary value based on maximum payload size that can be accommodated by underlying PCI. Update ingress pad boundary value based on smallest memory controller bus width possible. Enforce alignment for free list pointer start address. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>		2017-06-12 10:41:27 +01:00
..
bus	bus/fslmc: reduce the debug log messages	2017-06-12 10:41:26 +01:00
crypto	eal: introduce macro for always inline	2017-06-06 17:21:55 +02:00
event	eal: introduce macro for always inline	2017-06-06 17:21:55 +02:00
mempool	mempool/dpaa2: add hardware offloaded mempool	2017-04-19 15:37:37 +02:00
net	net/cxgbe: update Rx path for Chelsio T6	2017-06-12 10:41:27 +01:00
Makefile	crypto/dpaa2_sec: introduce poll mode driver	2017-04-20 11:32:45 +02:00