84fb33fec1
Replace use of RTE_MACHINE_CPUFLAG macros with regular compiler macros, which are more complete than those provided by DPDK, and as such it allows new instruction sets to be leveraged without having to do extra work to set them up in DPDK. Signed-off-by: Sean Morrissey <sean.morrissey@intel.com> Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: David Marchand <david.marchand@redhat.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2016-2017 Intel Corporation
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*/
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/* rte_efd_x86.h
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* This file holds all x86 specific EFD functions
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*/
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#include <immintrin.h>
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#if (RTE_EFD_VALUE_NUM_BITS == 8 || RTE_EFD_VALUE_NUM_BITS == 16 || \
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RTE_EFD_VALUE_NUM_BITS == 24 || RTE_EFD_VALUE_NUM_BITS == 32)
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#define EFD_LOAD_SI128(val) _mm_load_si128(val)
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#else
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#define EFD_LOAD_SI128(val) _mm_lddqu_si128(val)
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#endif
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static inline efd_value_t
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efd_lookup_internal_avx2(const efd_hashfunc_t *group_hash_idx,
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const efd_lookuptbl_t *group_lookup_table,
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const uint32_t hash_val_a, const uint32_t hash_val_b)
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{
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#ifdef __AVX2__
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efd_value_t value = 0;
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uint32_t i = 0;
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__m256i vhash_val_a = _mm256_set1_epi32(hash_val_a);
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__m256i vhash_val_b = _mm256_set1_epi32(hash_val_b);
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for (; i < RTE_EFD_VALUE_NUM_BITS; i += 8) {
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__m256i vhash_idx =
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_mm256_cvtepu16_epi32(EFD_LOAD_SI128(
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(__m128i const *) &group_hash_idx[i]));
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__m256i vlookup_table = _mm256_cvtepu16_epi32(
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EFD_LOAD_SI128((__m128i const *)
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&group_lookup_table[i]));
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__m256i vhash = _mm256_add_epi32(vhash_val_a,
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_mm256_mullo_epi32(vhash_idx, vhash_val_b));
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__m256i vbucket_idx = _mm256_srli_epi32(vhash,
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EFD_LOOKUPTBL_SHIFT);
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__m256i vresult = _mm256_srlv_epi32(vlookup_table,
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vbucket_idx);
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value |= (_mm256_movemask_ps(
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(__m256) _mm256_slli_epi32(vresult, 31))
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& ((1 << (RTE_EFD_VALUE_NUM_BITS - i)) - 1)) << i;
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}
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return value;
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#else
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RTE_SET_USED(group_hash_idx);
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RTE_SET_USED(group_lookup_table);
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RTE_SET_USED(hash_val_a);
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RTE_SET_USED(hash_val_b);
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/* Return dummy value, only to avoid compilation breakage */
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return 0;
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#endif
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}
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