2016-10-12 23:11:55 +00:00
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/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* NVMe over PCIe transport
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*/
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2016-11-15 02:33:24 +00:00
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#include <sys/mman.h>
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#include <signal.h>
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#include <sys/syscall.h>
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#include <sys/types.h>
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2016-10-12 23:11:55 +00:00
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#include "nvme_internal.h"
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2016-10-19 23:14:09 +00:00
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#define NVME_ADMIN_ENTRIES (128)
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2016-11-22 09:14:56 +00:00
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#define NVME_ADMIN_TRACKERS (64)
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2016-10-19 23:14:09 +00:00
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/*
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* NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
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* queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
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* will allow outstanding on an I/O qpair at any time. The only advantage in
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* having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
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* the contents of the submission and completion queues, it will show a longer
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* history of data.
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*/
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#define NVME_IO_ENTRIES (256)
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#define NVME_IO_TRACKERS (128)
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/*
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* NVME_MAX_SGL_DESCRIPTORS defines the maximum number of descriptors in one SGL
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* segment.
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*/
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#define NVME_MAX_SGL_DESCRIPTORS (253)
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#define NVME_MAX_PRP_LIST_ENTRIES (506)
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/*
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* For commands requiring more than 2 PRP entries, one PRP will be
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* embedded in the command (prp1), and the rest of the PRP entries
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* will be in a list pointed to by the command (prp2). This means
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* that real max number of PRP entries we support is 506+1, which
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* results in a max xfer size of 506*PAGE_SIZE.
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*/
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#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE
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2016-11-21 21:33:56 +00:00
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struct nvme_pcie_enum_ctx {
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spdk_nvme_probe_cb probe_cb;
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void *cb_ctx;
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};
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2016-10-19 23:14:09 +00:00
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2016-10-14 21:26:03 +00:00
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/* PCIe transport extensions for spdk_nvme_ctrlr */
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struct nvme_pcie_ctrlr {
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struct spdk_nvme_ctrlr ctrlr;
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/** NVMe MMIO register space */
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volatile struct spdk_nvme_registers *regs;
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2016-11-15 02:33:24 +00:00
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/** NVMe MMIO register size */
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uint64_t regs_size;
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2016-10-14 21:26:03 +00:00
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/* BAR mapping address which contains controller memory buffer */
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void *cmb_bar_virt_addr;
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/* BAR physical address which contains controller memory buffer */
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uint64_t cmb_bar_phys_addr;
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/* Controller memory buffer size in Bytes */
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uint64_t cmb_size;
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/* Current offset of controller memory buffer */
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uint64_t cmb_current_offset;
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/** stride in uint32_t units between doorbell registers (1 = 4 bytes, 2 = 8 bytes, ...) */
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uint32_t doorbell_stride_u32;
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2016-11-29 07:26:22 +00:00
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/* Opaque handle to associated PCI device. */
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struct spdk_pci_device *devhandle;
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2016-11-15 02:33:24 +00:00
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/* Flag to indicate the MMIO register has been remapped */
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bool is_remapped;
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2016-10-14 21:26:03 +00:00
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};
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2016-10-19 23:14:09 +00:00
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struct nvme_tracker {
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2016-12-10 22:39:54 +00:00
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TAILQ_ENTRY(nvme_tracker) tq_list;
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2016-10-19 23:14:09 +00:00
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struct nvme_request *req;
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uint16_t cid;
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uint16_t rsvd1: 15;
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uint16_t active: 1;
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uint32_t rsvd2;
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uint64_t prp_sgl_bus_addr;
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union {
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uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES];
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struct spdk_nvme_sgl_descriptor sgl[NVME_MAX_SGL_DESCRIPTORS];
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} u;
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uint64_t rsvd3;
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};
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/*
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* struct nvme_tracker must be exactly 4K so that the prp[] array does not cross a page boundary
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* and so that there is no padding required to meet alignment requirements.
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*/
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SPDK_STATIC_ASSERT(sizeof(struct nvme_tracker) == 4096, "nvme_tracker is not 4K");
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SPDK_STATIC_ASSERT((offsetof(struct nvme_tracker, u.sgl) & 7) == 0, "SGL must be Qword aligned");
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2016-10-19 22:29:39 +00:00
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/* PCIe transport extensions for spdk_nvme_qpair */
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struct nvme_pcie_qpair {
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/* Submission queue tail doorbell */
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volatile uint32_t *sq_tdbl;
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/* Completion queue head doorbell */
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volatile uint32_t *cq_hdbl;
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/* Submission queue */
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struct spdk_nvme_cmd *cmd;
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/* Completion queue */
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struct spdk_nvme_cpl *cpl;
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2016-12-10 22:39:54 +00:00
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TAILQ_HEAD(, nvme_tracker) free_tr;
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TAILQ_HEAD(nvme_outstanding_tr_head, nvme_tracker) outstanding_tr;
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2016-10-19 22:29:39 +00:00
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/* Array of trackers indexed by command ID. */
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struct nvme_tracker *tr;
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uint16_t sq_tail;
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uint16_t cq_head;
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uint8_t phase;
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bool is_enabled;
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/*
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* Base qpair structure.
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* This is located after the hot data in this structure so that the important parts of
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* nvme_pcie_qpair are in the same cache line.
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*/
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struct spdk_nvme_qpair qpair;
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/*
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* Fields below this point should not be touched on the normal I/O path.
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*/
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bool sq_in_cmb;
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uint64_t cmd_bus_addr;
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uint64_t cpl_bus_addr;
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};
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2016-11-28 22:25:05 +00:00
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static int nvme_pcie_qpair_destroy(struct spdk_nvme_qpair *qpair);
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2016-11-15 02:33:24 +00:00
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__thread struct nvme_pcie_ctrlr *g_thread_mmio_ctrlr = NULL;
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static volatile uint16_t g_signal_lock;
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static bool g_sigset = false;
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static void
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nvme_sigbus_fault_sighandler(int signum, siginfo_t *info, void *ctx)
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{
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void *map_address;
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if (!__sync_bool_compare_and_swap(&g_signal_lock, 0, 1)) {
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return;
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}
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if (g_thread_mmio_ctrlr) {
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if (!g_thread_mmio_ctrlr->is_remapped) {
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map_address = mmap((void *)g_thread_mmio_ctrlr->regs, g_thread_mmio_ctrlr->regs_size,
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PROT_READ | PROT_WRITE,
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MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED, -1, 0);
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if (map_address == MAP_FAILED) {
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SPDK_ERRLOG("mmap failed\n");
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g_signal_lock = 0;
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return;
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}
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memset(map_address, 0xFF, sizeof(struct spdk_nvme_registers));
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g_thread_mmio_ctrlr->regs = (volatile struct spdk_nvme_registers *)map_address;
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g_thread_mmio_ctrlr->is_remapped = true;
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}
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}
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g_signal_lock = 0;
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return;
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}
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static void
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nvme_pcie_ctrlr_setup_signal(void)
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{
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struct sigaction sa;
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sa.sa_sigaction = nvme_sigbus_fault_sighandler;
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sigemptyset(&sa.sa_mask);
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sa.sa_flags = SA_SIGINFO;
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sigaction(SIGBUS, &sa, NULL);
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}
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2016-10-14 21:26:03 +00:00
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static inline struct nvme_pcie_ctrlr *
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nvme_pcie_ctrlr(struct spdk_nvme_ctrlr *ctrlr)
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{
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2016-11-30 21:21:33 +00:00
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assert(ctrlr->trtype == SPDK_NVME_TRANSPORT_PCIE);
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2016-10-18 19:50:43 +00:00
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return (struct nvme_pcie_ctrlr *)((uintptr_t)ctrlr - offsetof(struct nvme_pcie_ctrlr, ctrlr));
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2016-10-14 21:26:03 +00:00
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}
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2016-10-19 22:29:39 +00:00
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static inline struct nvme_pcie_qpair *
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nvme_pcie_qpair(struct spdk_nvme_qpair *qpair)
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{
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2016-11-30 21:21:33 +00:00
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assert(qpair->trtype == SPDK_NVME_TRANSPORT_PCIE);
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2016-10-19 22:29:39 +00:00
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return (struct nvme_pcie_qpair *)((uintptr_t)qpair - offsetof(struct nvme_pcie_qpair, qpair));
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}
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2016-11-03 22:34:35 +00:00
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int
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2016-10-28 18:11:45 +00:00
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nvme_pcie_ctrlr_get_pci_id(struct spdk_nvme_ctrlr *ctrlr, struct spdk_pci_id *pci_id)
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2016-10-12 23:18:13 +00:00
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{
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assert(ctrlr != NULL);
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assert(pci_id != NULL);
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2016-10-31 23:55:14 +00:00
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*pci_id = ctrlr->probe_info.pci_id;
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2016-10-12 23:18:13 +00:00
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return 0;
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}
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2016-10-13 00:00:54 +00:00
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static volatile void *
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nvme_pcie_reg_addr(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset)
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{
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2016-10-14 21:26:03 +00:00
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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return (volatile void *)((uintptr_t)pctrlr->regs + offset);
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2016-10-13 00:00:54 +00:00
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}
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2016-11-03 22:34:35 +00:00
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int
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2016-10-13 00:00:54 +00:00
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nvme_pcie_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value)
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{
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2016-11-15 02:33:24 +00:00
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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2016-10-13 00:00:54 +00:00
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assert(offset <= sizeof(struct spdk_nvme_registers) - 4);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = pctrlr;
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2016-10-13 00:00:54 +00:00
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spdk_mmio_write_4(nvme_pcie_reg_addr(ctrlr, offset), value);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = NULL;
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2016-10-13 00:00:54 +00:00
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return 0;
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}
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2016-11-03 22:34:35 +00:00
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int
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2016-10-13 00:00:54 +00:00
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nvme_pcie_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value)
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{
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2016-11-15 02:33:24 +00:00
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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2016-10-13 00:00:54 +00:00
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assert(offset <= sizeof(struct spdk_nvme_registers) - 8);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = pctrlr;
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2016-10-13 00:00:54 +00:00
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spdk_mmio_write_8(nvme_pcie_reg_addr(ctrlr, offset), value);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = NULL;
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2016-10-13 00:00:54 +00:00
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return 0;
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}
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2016-11-03 22:34:35 +00:00
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int
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2016-10-13 00:00:54 +00:00
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nvme_pcie_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value)
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{
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2016-11-15 02:33:24 +00:00
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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2016-10-13 00:00:54 +00:00
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assert(offset <= sizeof(struct spdk_nvme_registers) - 4);
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assert(value != NULL);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = pctrlr;
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2016-10-13 00:00:54 +00:00
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*value = spdk_mmio_read_4(nvme_pcie_reg_addr(ctrlr, offset));
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = NULL;
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if (~(*value) == 0) {
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return -1;
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}
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2016-10-13 00:00:54 +00:00
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return 0;
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}
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2016-11-03 22:34:35 +00:00
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int
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2016-10-13 00:00:54 +00:00
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nvme_pcie_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value)
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{
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2016-11-15 02:33:24 +00:00
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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2016-10-13 00:00:54 +00:00
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assert(offset <= sizeof(struct spdk_nvme_registers) - 8);
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assert(value != NULL);
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2016-11-15 02:33:24 +00:00
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g_thread_mmio_ctrlr = pctrlr;
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2016-10-13 00:00:54 +00:00
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*value = spdk_mmio_read_8(nvme_pcie_reg_addr(ctrlr, offset));
|
2016-11-15 02:33:24 +00:00
|
|
|
g_thread_mmio_ctrlr = NULL;
|
|
|
|
if (~(*value) == 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-13 00:00:54 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:42:21 +00:00
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_set_asq(struct nvme_pcie_ctrlr *pctrlr, uint64_t value)
|
|
|
|
{
|
|
|
|
return nvme_pcie_ctrlr_set_reg_8(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, asq),
|
|
|
|
value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_set_acq(struct nvme_pcie_ctrlr *pctrlr, uint64_t value)
|
|
|
|
{
|
|
|
|
return nvme_pcie_ctrlr_set_reg_8(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, acq),
|
|
|
|
value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_set_aqa(struct nvme_pcie_ctrlr *pctrlr, const union spdk_nvme_aqa_register *aqa)
|
|
|
|
{
|
|
|
|
return nvme_pcie_ctrlr_set_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, aqa.raw),
|
|
|
|
aqa->raw);
|
|
|
|
}
|
|
|
|
|
2016-10-13 23:08:22 +00:00
|
|
|
static int
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_get_cmbloc(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_cmbloc_register *cmbloc)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
2016-10-14 21:26:03 +00:00
|
|
|
return nvme_pcie_ctrlr_get_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, cmbloc.raw),
|
2016-10-13 23:08:22 +00:00
|
|
|
&cmbloc->raw);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_get_cmbsz(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_cmbsz_register *cmbsz)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
2016-10-14 21:26:03 +00:00
|
|
|
return nvme_pcie_ctrlr_get_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
|
2016-10-13 23:08:22 +00:00
|
|
|
&cmbsz->raw);
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
uint32_t
|
2016-10-19 23:14:09 +00:00
|
|
|
nvme_pcie_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
|
|
|
return NVME_MAX_XFER_SIZE;
|
|
|
|
}
|
|
|
|
|
2016-10-13 23:08:22 +00:00
|
|
|
static void
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_map_cmb(struct nvme_pcie_ctrlr *pctrlr)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
void *addr;
|
|
|
|
uint32_t bir;
|
|
|
|
union spdk_nvme_cmbsz_register cmbsz;
|
|
|
|
union spdk_nvme_cmbloc_register cmbloc;
|
|
|
|
uint64_t size, unit_size, offset, bar_size, bar_phys_addr;
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
if (nvme_pcie_ctrlr_get_cmbsz(pctrlr, &cmbsz) ||
|
|
|
|
nvme_pcie_ctrlr_get_cmbloc(pctrlr, &cmbloc)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("get registers failed\n");
|
2016-10-13 23:08:22 +00:00
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!cmbsz.bits.sz)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
bir = cmbloc.bits.bir;
|
|
|
|
/* Values 0 2 3 4 5 are valid for BAR */
|
|
|
|
if (bir > 5 || bir == 1)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
/* unit size for 4KB/64KB/1MB/16MB/256MB/4GB/64GB */
|
|
|
|
unit_size = (uint64_t)1 << (12 + 4 * cmbsz.bits.szu);
|
|
|
|
/* controller memory buffer size in Bytes */
|
|
|
|
size = unit_size * cmbsz.bits.sz;
|
|
|
|
/* controller memory buffer offset from BAR in Bytes */
|
|
|
|
offset = unit_size * cmbloc.bits.ofst;
|
|
|
|
|
2016-11-29 07:26:22 +00:00
|
|
|
rc = spdk_pci_device_map_bar(pctrlr->devhandle, bir, &addr,
|
2016-10-13 23:08:22 +00:00
|
|
|
&bar_phys_addr, &bar_size);
|
|
|
|
if ((rc != 0) || addr == NULL) {
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (offset > bar_size) {
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size > bar_size - offset) {
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->cmb_bar_virt_addr = addr;
|
|
|
|
pctrlr->cmb_bar_phys_addr = bar_phys_addr;
|
|
|
|
pctrlr->cmb_size = size;
|
|
|
|
pctrlr->cmb_current_offset = offset;
|
2016-10-13 23:08:22 +00:00
|
|
|
|
|
|
|
if (!cmbsz.bits.sqs) {
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->ctrlr.opts.use_cmb_sqs = false;
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
exit:
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->cmb_bar_virt_addr = NULL;
|
|
|
|
pctrlr->ctrlr.opts.use_cmb_sqs = false;
|
2016-10-13 23:08:22 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_unmap_cmb(struct nvme_pcie_ctrlr *pctrlr)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
union spdk_nvme_cmbloc_register cmbloc;
|
2016-10-14 21:26:03 +00:00
|
|
|
void *addr = pctrlr->cmb_bar_virt_addr;
|
2016-10-13 23:08:22 +00:00
|
|
|
|
|
|
|
if (addr) {
|
2016-10-14 21:26:03 +00:00
|
|
|
if (nvme_pcie_ctrlr_get_cmbloc(pctrlr, &cmbloc)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("get_cmbloc() failed\n");
|
2016-10-13 23:08:22 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
2016-11-29 07:26:22 +00:00
|
|
|
rc = spdk_pci_device_unmap_bar(pctrlr->devhandle, cmbloc.bits.bir, addr);
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_alloc_cmb(struct spdk_nvme_ctrlr *ctrlr, uint64_t length, uint64_t aligned,
|
|
|
|
uint64_t *offset)
|
|
|
|
{
|
2016-10-14 21:26:03 +00:00
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
|
2016-10-13 23:08:22 +00:00
|
|
|
uint64_t round_offset;
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
round_offset = pctrlr->cmb_current_offset;
|
2016-10-13 23:08:22 +00:00
|
|
|
round_offset = (round_offset + (aligned - 1)) & ~(aligned - 1);
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
if (round_offset + length > pctrlr->cmb_size)
|
2016-10-13 23:08:22 +00:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
*offset = round_offset;
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->cmb_current_offset = round_offset + length;
|
2016-10-13 23:08:22 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_allocate_bars(struct nvme_pcie_ctrlr *pctrlr)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
void *addr;
|
|
|
|
uint64_t phys_addr, size;
|
|
|
|
|
2016-11-29 07:26:22 +00:00
|
|
|
rc = spdk_pci_device_map_bar(pctrlr->devhandle, 0, &addr,
|
2016-10-13 23:08:22 +00:00
|
|
|
&phys_addr, &size);
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->regs = (volatile struct spdk_nvme_registers *)addr;
|
|
|
|
if ((pctrlr->regs == NULL) || (rc != 0)) {
|
2016-10-13 23:08:22 +00:00
|
|
|
SPDK_ERRLOG("nvme_pcicfg_map_bar failed with rc %d or bar %p\n",
|
2016-10-14 21:26:03 +00:00
|
|
|
rc, pctrlr->regs);
|
2016-10-13 23:08:22 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-11-15 02:33:24 +00:00
|
|
|
pctrlr->regs_size = size;
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_map_cmb(pctrlr);
|
2016-10-13 23:08:22 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_free_bars(struct nvme_pcie_ctrlr *pctrlr)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
|
|
|
int rc = 0;
|
2016-10-14 21:26:03 +00:00
|
|
|
void *addr = (void *)pctrlr->regs;
|
2016-10-13 23:08:22 +00:00
|
|
|
|
2016-11-18 15:52:43 +00:00
|
|
|
if (pctrlr->ctrlr.is_removed) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
rc = nvme_pcie_ctrlr_unmap_cmb(pctrlr);
|
2016-10-13 23:08:22 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
SPDK_ERRLOG("nvme_ctrlr_unmap_cmb failed with error code %d\n", rc);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr) {
|
2016-11-15 02:33:24 +00:00
|
|
|
/* NOTE: addr may have been remapped here. We're relying on DPDK to call
|
|
|
|
* munmap internally.
|
|
|
|
*/
|
2016-11-29 07:26:22 +00:00
|
|
|
rc = spdk_pci_device_unmap_bar(pctrlr->devhandle, 0, addr);
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:29:16 +00:00
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_construct_admin_qpair(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair;
|
|
|
|
|
|
|
|
pqpair = spdk_zmalloc(sizeof(*pqpair), 64, NULL);
|
|
|
|
if (pqpair == NULL) {
|
2016-10-19 20:29:16 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
ctrlr->adminq = &pqpair->qpair;
|
|
|
|
|
2016-10-19 20:29:16 +00:00
|
|
|
return nvme_qpair_construct(ctrlr->adminq,
|
|
|
|
0, /* qpair ID */
|
|
|
|
NVME_ADMIN_ENTRIES,
|
2016-10-26 01:28:20 +00:00
|
|
|
ctrlr,
|
|
|
|
SPDK_NVME_QPRIO_URGENT);
|
2016-10-19 20:29:16 +00:00
|
|
|
}
|
|
|
|
|
2016-11-15 05:42:59 +00:00
|
|
|
/* This function must only be called while holding g_spdk_nvme_driver->lock */
|
|
|
|
static int
|
|
|
|
pcie_nvme_enum_cb(void *ctx, struct spdk_pci_device *pci_dev)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_probe_info probe_info = {};
|
2016-11-21 21:33:56 +00:00
|
|
|
struct nvme_pcie_enum_ctx *enum_ctx = ctx;
|
|
|
|
struct spdk_nvme_ctrlr *ctrlr;
|
2016-11-15 06:54:52 +00:00
|
|
|
int rc = 0;
|
2016-11-15 05:42:59 +00:00
|
|
|
|
2016-12-06 17:42:33 +00:00
|
|
|
probe_info.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
|
2016-11-15 05:42:59 +00:00
|
|
|
probe_info.pci_addr = spdk_pci_device_get_addr(pci_dev);
|
|
|
|
probe_info.pci_id = spdk_pci_device_get_id(pci_dev);
|
|
|
|
|
2016-11-21 21:33:56 +00:00
|
|
|
/* Verify that this controller is not already attached */
|
|
|
|
TAILQ_FOREACH(ctrlr, &g_spdk_nvme_driver->attached_ctrlrs, tailq) {
|
|
|
|
/* NOTE: In the case like multi-process environment where the device handle is
|
|
|
|
* different per each process, we compare by BDF to determine whether it is the
|
|
|
|
* same controller.
|
|
|
|
*/
|
|
|
|
if (spdk_pci_addr_compare(&probe_info.pci_addr, &ctrlr->probe_info.pci_addr) == 0) {
|
2016-11-15 06:54:52 +00:00
|
|
|
if (!spdk_process_is_primary()) {
|
|
|
|
rc = nvme_ctrlr_add_process(ctrlr, pci_dev);
|
|
|
|
}
|
|
|
|
return rc;
|
2016-11-21 21:33:56 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-06 17:42:33 +00:00
|
|
|
return nvme_ctrlr_probe(&probe_info, pci_dev,
|
|
|
|
enum_ctx->probe_cb, enum_ctx->cb_ctx);
|
2016-11-15 05:42:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2016-12-05 17:59:12 +00:00
|
|
|
nvme_pcie_ctrlr_scan(const struct spdk_nvme_transport_id *trid,
|
2016-12-06 17:36:34 +00:00
|
|
|
void *cb_ctx,
|
|
|
|
spdk_nvme_probe_cb probe_cb,
|
|
|
|
spdk_nvme_remove_cb remove_cb)
|
2016-11-15 05:42:59 +00:00
|
|
|
{
|
2016-11-21 21:33:56 +00:00
|
|
|
struct nvme_pcie_enum_ctx enum_ctx;
|
|
|
|
|
|
|
|
enum_ctx.probe_cb = probe_cb;
|
|
|
|
enum_ctx.cb_ctx = cb_ctx;
|
2016-12-05 17:59:12 +00:00
|
|
|
|
|
|
|
return spdk_pci_nvme_enumerate(pcie_nvme_enum_cb, &enum_ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nvme_pcie_ctrlr_attach(enum spdk_nvme_transport_type trtype,
|
|
|
|
spdk_nvme_probe_cb probe_cb, void *cb_ctx,
|
|
|
|
struct spdk_pci_addr *pci_addr)
|
|
|
|
{
|
|
|
|
struct nvme_pcie_enum_ctx enum_ctx;
|
|
|
|
|
|
|
|
enum_ctx.probe_cb = probe_cb;
|
|
|
|
enum_ctx.cb_ctx = cb_ctx;
|
|
|
|
|
|
|
|
return spdk_pci_nvme_device_attach(pcie_nvme_enum_cb, &enum_ctx, pci_addr);
|
2016-11-15 05:42:59 +00:00
|
|
|
}
|
|
|
|
|
2016-11-30 21:21:33 +00:00
|
|
|
struct spdk_nvme_ctrlr *nvme_pcie_ctrlr_construct(enum spdk_nvme_transport_type trtype,
|
2016-11-28 23:26:04 +00:00
|
|
|
const struct spdk_nvme_ctrlr_opts *opts,
|
|
|
|
const struct spdk_nvme_probe_info *probe_info,
|
2016-11-03 22:34:35 +00:00
|
|
|
void *devhandle)
|
2016-10-13 23:08:22 +00:00
|
|
|
{
|
2016-10-18 19:50:43 +00:00
|
|
|
struct spdk_pci_device *pci_dev = devhandle;
|
|
|
|
struct nvme_pcie_ctrlr *pctrlr;
|
2016-10-13 23:08:22 +00:00
|
|
|
union spdk_nvme_cap_register cap;
|
|
|
|
uint32_t cmd_reg;
|
|
|
|
int rc;
|
|
|
|
|
2016-10-18 19:50:43 +00:00
|
|
|
pctrlr = spdk_zmalloc(sizeof(struct nvme_pcie_ctrlr), 64, NULL);
|
|
|
|
if (pctrlr == NULL) {
|
|
|
|
SPDK_ERRLOG("could not allocate ctrlr\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-11-15 02:33:24 +00:00
|
|
|
pctrlr->is_remapped = false;
|
2016-11-18 15:52:43 +00:00
|
|
|
pctrlr->ctrlr.is_removed = false;
|
2016-11-30 21:21:33 +00:00
|
|
|
pctrlr->ctrlr.trtype = SPDK_NVME_TRANSPORT_PCIE;
|
2016-11-29 07:26:22 +00:00
|
|
|
pctrlr->devhandle = devhandle;
|
2016-11-28 23:26:04 +00:00
|
|
|
pctrlr->ctrlr.opts = *opts;
|
|
|
|
pctrlr->ctrlr.probe_info = *probe_info;
|
2016-10-18 19:50:43 +00:00
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
rc = nvme_pcie_ctrlr_allocate_bars(pctrlr);
|
2016-10-13 23:08:22 +00:00
|
|
|
if (rc != 0) {
|
2016-10-18 19:50:43 +00:00
|
|
|
spdk_free(pctrlr);
|
|
|
|
return NULL;
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable PCI busmaster and disable INTx */
|
2016-10-18 19:50:43 +00:00
|
|
|
spdk_pci_device_cfg_read32(pci_dev, &cmd_reg, 4);
|
2016-10-13 23:08:22 +00:00
|
|
|
cmd_reg |= 0x404;
|
2016-10-18 19:50:43 +00:00
|
|
|
spdk_pci_device_cfg_write32(pci_dev, cmd_reg, 4);
|
2016-10-13 23:08:22 +00:00
|
|
|
|
2016-10-18 19:50:43 +00:00
|
|
|
if (nvme_ctrlr_get_cap(&pctrlr->ctrlr, &cap)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("get_cap() failed\n");
|
2016-10-18 19:50:43 +00:00
|
|
|
spdk_free(pctrlr);
|
|
|
|
return NULL;
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
|
2016-10-19 20:18:27 +00:00
|
|
|
pctrlr->ctrlr.cap = cap;
|
|
|
|
|
2016-10-13 23:08:22 +00:00
|
|
|
/* Doorbell stride is 2 ^ (dstrd + 2),
|
|
|
|
* but we want multiples of 4, so drop the + 2 */
|
2016-10-14 21:26:03 +00:00
|
|
|
pctrlr->doorbell_stride_u32 = 1 << cap.bits.dstrd;
|
2016-10-13 23:08:22 +00:00
|
|
|
|
2016-10-18 19:50:43 +00:00
|
|
|
rc = nvme_ctrlr_construct(&pctrlr->ctrlr);
|
|
|
|
if (rc != 0) {
|
2016-10-19 00:34:33 +00:00
|
|
|
nvme_ctrlr_destruct(&pctrlr->ctrlr);
|
2016-10-18 19:50:43 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-12-02 16:31:06 +00:00
|
|
|
pctrlr->ctrlr.quirks = nvme_get_quirks(&probe_info->pci_id);
|
|
|
|
|
2016-10-19 20:29:16 +00:00
|
|
|
rc = nvme_pcie_ctrlr_construct_admin_qpair(&pctrlr->ctrlr);
|
|
|
|
if (rc != 0) {
|
|
|
|
nvme_ctrlr_destruct(&pctrlr->ctrlr);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-10-18 01:03:24 +00:00
|
|
|
/* Construct the primary process properties */
|
|
|
|
rc = nvme_ctrlr_add_process(&pctrlr->ctrlr, pci_dev);
|
|
|
|
if (rc != 0) {
|
|
|
|
nvme_ctrlr_destruct(&pctrlr->ctrlr);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-11-15 02:33:24 +00:00
|
|
|
if (g_sigset != true) {
|
|
|
|
nvme_pcie_ctrlr_setup_signal();
|
|
|
|
g_sigset = true;
|
|
|
|
}
|
|
|
|
|
2016-10-18 19:50:43 +00:00
|
|
|
return &pctrlr->ctrlr;
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-19 20:42:21 +00:00
|
|
|
nvme_pcie_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *padminq = nvme_pcie_qpair(ctrlr->adminq);
|
2016-10-19 20:42:21 +00:00
|
|
|
union spdk_nvme_aqa_register aqa;
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (nvme_pcie_ctrlr_set_asq(pctrlr, padminq->cmd_bus_addr)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("set_asq() failed\n");
|
2016-10-19 20:42:21 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (nvme_pcie_ctrlr_set_acq(pctrlr, padminq->cpl_bus_addr)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("set_acq() failed\n");
|
2016-10-19 20:42:21 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
aqa.raw = 0;
|
|
|
|
/* acqs and asqs are 0-based. */
|
|
|
|
aqa.bits.acqs = ctrlr->adminq->num_entries - 1;
|
|
|
|
aqa.bits.asqs = ctrlr->adminq->num_entries - 1;
|
|
|
|
|
|
|
|
if (nvme_pcie_ctrlr_set_aqa(pctrlr, &aqa)) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("set_aqa() failed\n");
|
2016-10-19 20:42:21 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 23:08:22 +00:00
|
|
|
nvme_pcie_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
|
|
|
|
{
|
2016-10-14 21:26:03 +00:00
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
|
|
|
|
|
2016-10-19 20:29:16 +00:00
|
|
|
if (ctrlr->adminq) {
|
2016-11-28 22:25:05 +00:00
|
|
|
nvme_pcie_qpair_destroy(ctrlr->adminq);
|
2016-10-19 20:29:16 +00:00
|
|
|
}
|
|
|
|
|
2016-11-15 06:54:52 +00:00
|
|
|
nvme_ctrlr_free_processes(ctrlr);
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
nvme_pcie_ctrlr_free_bars(pctrlr);
|
2016-11-15 01:53:14 +00:00
|
|
|
spdk_pci_device_detach(pctrlr->devhandle);
|
2016-10-18 19:50:43 +00:00
|
|
|
spdk_free(pctrlr);
|
2016-11-03 22:34:35 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-13 23:08:22 +00:00
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
static void
|
|
|
|
nvme_qpair_construct_tracker(struct nvme_tracker *tr, uint16_t cid, uint64_t phys_addr)
|
|
|
|
{
|
|
|
|
tr->prp_sgl_bus_addr = phys_addr + offsetof(struct nvme_tracker, u.prp);
|
|
|
|
tr->cid = cid;
|
|
|
|
tr->active = false;
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_reset(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
|
|
|
|
pqpair->sq_tail = pqpair->cq_head = 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* First time through the completion queue, HW will set phase
|
|
|
|
* bit on completions to 1. So set this to 1 here, indicating
|
|
|
|
* we're looking for a 1 to know which entries have completed.
|
|
|
|
* we'll toggle the bit each time when the completion queue
|
|
|
|
* rolls over.
|
|
|
|
*/
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->phase = 1;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
memset(pqpair->cmd, 0,
|
2016-10-13 22:23:55 +00:00
|
|
|
qpair->num_entries * sizeof(struct spdk_nvme_cmd));
|
2016-10-19 22:29:39 +00:00
|
|
|
memset(pqpair->cpl, 0,
|
2016-10-13 22:23:55 +00:00
|
|
|
qpair->num_entries * sizeof(struct spdk_nvme_cpl));
|
2016-11-03 22:34:35 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_construct(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
|
2016-10-14 21:26:03 +00:00
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
2016-10-13 22:23:55 +00:00
|
|
|
struct nvme_tracker *tr;
|
|
|
|
uint16_t i;
|
|
|
|
volatile uint32_t *doorbell_base;
|
|
|
|
uint64_t phys_addr = 0;
|
|
|
|
uint64_t offset;
|
|
|
|
uint16_t num_trackers;
|
|
|
|
|
|
|
|
if (qpair->id == 0) {
|
|
|
|
num_trackers = NVME_ADMIN_TRACKERS;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* No need to have more trackers than entries in the submit queue.
|
|
|
|
* Note also that for a queue size of N, we can only have (N-1)
|
|
|
|
* commands outstanding, hence the "-1" here.
|
|
|
|
*/
|
|
|
|
num_trackers = nvme_min(NVME_IO_TRACKERS, qpair->num_entries - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(num_trackers != 0);
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->sq_in_cmb = false;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
/* cmd and cpl rings must be aligned on 4KB boundaries. */
|
|
|
|
if (ctrlr->opts.use_cmb_sqs) {
|
2016-10-13 23:08:22 +00:00
|
|
|
if (nvme_pcie_ctrlr_alloc_cmb(ctrlr, qpair->num_entries * sizeof(struct spdk_nvme_cmd),
|
|
|
|
0x1000, &offset) == 0) {
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->cmd = pctrlr->cmb_bar_virt_addr + offset;
|
|
|
|
pqpair->cmd_bus_addr = pctrlr->cmb_bar_phys_addr + offset;
|
|
|
|
pqpair->sq_in_cmb = true;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
}
|
2016-10-19 22:29:39 +00:00
|
|
|
if (pqpair->sq_in_cmb == false) {
|
|
|
|
pqpair->cmd = spdk_zmalloc(qpair->num_entries * sizeof(struct spdk_nvme_cmd),
|
|
|
|
0x1000,
|
|
|
|
&pqpair->cmd_bus_addr);
|
|
|
|
if (pqpair->cmd == NULL) {
|
2016-10-13 22:23:55 +00:00
|
|
|
SPDK_ERRLOG("alloc qpair_cmd failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->cpl = spdk_zmalloc(qpair->num_entries * sizeof(struct spdk_nvme_cpl),
|
|
|
|
0x1000,
|
|
|
|
&pqpair->cpl_bus_addr);
|
|
|
|
if (pqpair->cpl == NULL) {
|
2016-10-13 22:23:55 +00:00
|
|
|
SPDK_ERRLOG("alloc qpair_cpl failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-10-14 21:26:03 +00:00
|
|
|
doorbell_base = &pctrlr->regs->doorbell[0].sq_tdbl;
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->sq_tdbl = doorbell_base + (2 * qpair->id + 0) * pctrlr->doorbell_stride_u32;
|
|
|
|
pqpair->cq_hdbl = doorbell_base + (2 * qpair->id + 1) * pctrlr->doorbell_stride_u32;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Reserve space for all of the trackers in a single allocation.
|
|
|
|
* struct nvme_tracker must be padded so that its size is already a power of 2.
|
|
|
|
* This ensures the PRP list embedded in the nvme_tracker object will not span a
|
|
|
|
* 4KB boundary, while allowing access to trackers in tr[] via normal array indexing.
|
|
|
|
*/
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->tr = spdk_zmalloc(num_trackers * sizeof(*tr), sizeof(*tr), &phys_addr);
|
|
|
|
if (pqpair->tr == NULL) {
|
2016-10-13 22:23:55 +00:00
|
|
|
SPDK_ERRLOG("nvme_tr failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
TAILQ_INIT(&pqpair->free_tr);
|
|
|
|
TAILQ_INIT(&pqpair->outstanding_tr);
|
2016-10-19 22:29:39 +00:00
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
for (i = 0; i < num_trackers; i++) {
|
2016-10-19 22:29:39 +00:00
|
|
|
tr = &pqpair->tr[i];
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_qpair_construct_tracker(tr, i, phys_addr);
|
2016-12-10 22:39:54 +00:00
|
|
|
TAILQ_INSERT_HEAD(&pqpair->free_tr, tr, tq_list);
|
2016-10-13 22:23:55 +00:00
|
|
|
phys_addr += sizeof(struct nvme_tracker);
|
|
|
|
}
|
|
|
|
|
|
|
|
nvme_pcie_qpair_reset(qpair);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
nvme_pcie_copy_command(struct spdk_nvme_cmd *dst, const struct spdk_nvme_cmd *src)
|
|
|
|
{
|
|
|
|
/* dst and src are known to be non-overlapping and 64-byte aligned. */
|
|
|
|
#if defined(__AVX__)
|
|
|
|
__m256i *d256 = (__m256i *)dst;
|
|
|
|
const __m256i *s256 = (const __m256i *)src;
|
|
|
|
|
|
|
|
_mm256_store_si256(&d256[0], _mm256_load_si256(&s256[0]));
|
|
|
|
_mm256_store_si256(&d256[1], _mm256_load_si256(&s256[1]));
|
|
|
|
#elif defined(__SSE2__)
|
|
|
|
__m128i *d128 = (__m128i *)dst;
|
|
|
|
const __m128i *s128 = (const __m128i *)src;
|
|
|
|
|
|
|
|
_mm_store_si128(&d128[0], _mm_load_si128(&s128[0]));
|
|
|
|
_mm_store_si128(&d128[1], _mm_load_si128(&s128[1]));
|
|
|
|
_mm_store_si128(&d128[2], _mm_load_si128(&s128[2]));
|
|
|
|
_mm_store_si128(&d128[3], _mm_load_si128(&s128[3]));
|
|
|
|
#else
|
|
|
|
*dst = *src;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2016-11-22 09:31:46 +00:00
|
|
|
/**
|
|
|
|
* Note: the ctrlr_lock must be held when calling this function.
|
|
|
|
*/
|
2016-10-18 01:03:24 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_insert_pending_admin_request(struct spdk_nvme_qpair *qpair,
|
|
|
|
struct nvme_request *req, struct spdk_nvme_cpl *cpl)
|
|
|
|
{
|
2016-11-17 01:54:17 +00:00
|
|
|
struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
|
|
|
|
struct nvme_request *active_req = req;
|
2016-11-24 02:28:12 +00:00
|
|
|
struct spdk_nvme_ctrlr_process *active_proc;
|
2016-11-17 01:54:17 +00:00
|
|
|
bool pending_on_proc = false;
|
2016-10-18 01:03:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The admin request is from another process. Move to the per
|
|
|
|
* process list for that process to handle it later.
|
|
|
|
*/
|
|
|
|
assert(nvme_qpair_is_admin_queue(qpair));
|
|
|
|
assert(active_req->pid != getpid());
|
|
|
|
|
2016-11-24 02:28:12 +00:00
|
|
|
TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
|
2016-10-18 01:03:24 +00:00
|
|
|
if (active_proc->pid == active_req->pid) {
|
|
|
|
/* Saved the original completion information */
|
|
|
|
memcpy(&active_req->cpl, cpl, sizeof(*cpl));
|
|
|
|
STAILQ_INSERT_TAIL(&active_proc->active_reqs, active_req, stailq);
|
|
|
|
pending_on_proc = true;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pending_on_proc == false) {
|
2016-11-24 02:28:12 +00:00
|
|
|
SPDK_ERRLOG("The owning process (pid %d) is not found. Drop the request.\n",
|
|
|
|
active_req->pid);
|
2016-10-18 01:03:24 +00:00
|
|
|
|
|
|
|
nvme_free_request(active_req);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-22 09:31:46 +00:00
|
|
|
/**
|
|
|
|
* Note: the ctrlr_lock must be held when calling this function.
|
|
|
|
*/
|
2016-10-18 01:03:24 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_complete_pending_admin_request(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
|
|
|
|
struct nvme_request *req, *tmp_req;
|
|
|
|
bool proc_found = false;
|
|
|
|
pid_t pid = getpid();
|
2016-11-17 01:54:17 +00:00
|
|
|
struct spdk_nvme_ctrlr_process *proc;
|
2016-10-18 01:03:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check whether there is any pending admin request from
|
|
|
|
* other active processes.
|
|
|
|
*/
|
|
|
|
assert(nvme_qpair_is_admin_queue(qpair));
|
|
|
|
|
|
|
|
TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
|
|
|
|
if (proc->pid == pid) {
|
|
|
|
proc_found = true;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (proc_found == false) {
|
2016-11-24 02:28:12 +00:00
|
|
|
SPDK_ERRLOG("the active process (pid %d) is not found for this controller.\n", pid);
|
2016-10-18 01:03:24 +00:00
|
|
|
assert(proc_found);
|
|
|
|
}
|
|
|
|
|
|
|
|
STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
|
|
|
|
STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
|
|
|
|
|
|
|
|
assert(req->pid == pid);
|
|
|
|
|
|
|
|
if (req->cb_fn) {
|
|
|
|
req->cb_fn(req->cb_arg, &req->cpl);
|
|
|
|
}
|
|
|
|
|
|
|
|
nvme_free_request(req);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_submit_tracker(struct spdk_nvme_qpair *qpair, struct nvme_tracker *tr)
|
|
|
|
{
|
|
|
|
struct nvme_request *req;
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
2016-11-15 02:33:24 +00:00
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(qpair->ctrlr);
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
req = tr->req;
|
2016-10-19 22:29:39 +00:00
|
|
|
pqpair->tr[tr->cid].active = true;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
/* Copy the command from the tracker to the submission queue. */
|
2016-10-19 22:29:39 +00:00
|
|
|
nvme_pcie_copy_command(&pqpair->cmd[pqpair->sq_tail], &req->cmd);
|
2016-10-13 22:23:55 +00:00
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (++pqpair->sq_tail == qpair->num_entries) {
|
|
|
|
pqpair->sq_tail = 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
spdk_wmb();
|
2016-11-15 02:33:24 +00:00
|
|
|
g_thread_mmio_ctrlr = pctrlr;
|
2016-10-19 22:29:39 +00:00
|
|
|
spdk_mmio_write_4(pqpair->sq_tdbl, pqpair->sq_tail);
|
2016-11-15 02:33:24 +00:00
|
|
|
g_thread_mmio_ctrlr = NULL;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_complete_tracker(struct spdk_nvme_qpair *qpair, struct nvme_tracker *tr,
|
|
|
|
struct spdk_nvme_cpl *cpl, bool print_on_error)
|
|
|
|
{
|
2016-10-18 01:03:24 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
struct nvme_request *req;
|
|
|
|
bool retry, error, was_active;
|
|
|
|
bool req_from_current_proc = true;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
req = tr->req;
|
|
|
|
|
|
|
|
assert(req != NULL);
|
|
|
|
|
|
|
|
error = spdk_nvme_cpl_is_error(cpl);
|
|
|
|
retry = error && nvme_completion_is_retry(cpl) &&
|
|
|
|
req->retries < spdk_nvme_retry_count;
|
|
|
|
|
|
|
|
if (error && print_on_error) {
|
|
|
|
nvme_qpair_print_command(qpair, &req->cmd);
|
|
|
|
nvme_qpair_print_completion(qpair, cpl);
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
was_active = pqpair->tr[cpl->cid].active;
|
|
|
|
pqpair->tr[cpl->cid].active = false;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
assert(cpl->cid == req->cmd.cid);
|
|
|
|
|
|
|
|
if (retry) {
|
|
|
|
req->retries++;
|
|
|
|
nvme_pcie_qpair_submit_tracker(qpair, tr);
|
|
|
|
} else {
|
2016-11-24 02:34:41 +00:00
|
|
|
if (was_active) {
|
2016-10-18 01:03:24 +00:00
|
|
|
/* Only check admin requests from different processes. */
|
|
|
|
if (nvme_qpair_is_admin_queue(qpair) && req->pid != getpid()) {
|
|
|
|
req_from_current_proc = false;
|
|
|
|
nvme_pcie_qpair_insert_pending_admin_request(qpair, req, cpl);
|
|
|
|
} else {
|
2016-11-24 02:34:41 +00:00
|
|
|
if (req->cb_fn) {
|
|
|
|
req->cb_fn(req->cb_arg, cpl);
|
|
|
|
}
|
2016-10-18 01:03:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req_from_current_proc == true) {
|
|
|
|
nvme_free_request(req);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
tr->req = NULL;
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
TAILQ_REMOVE(&pqpair->outstanding_tr, tr, tq_list);
|
|
|
|
TAILQ_INSERT_HEAD(&pqpair->free_tr, tr, tq_list);
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If the controller is in the middle of resetting, don't
|
|
|
|
* try to submit queued requests here - let the reset logic
|
|
|
|
* handle that instead.
|
|
|
|
*/
|
|
|
|
if (!STAILQ_EMPTY(&qpair->queued_req) &&
|
|
|
|
!qpair->ctrlr->is_resetting) {
|
|
|
|
req = STAILQ_FIRST(&qpair->queued_req);
|
|
|
|
STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq);
|
|
|
|
nvme_qpair_submit_request(qpair, req);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_manual_complete_tracker(struct spdk_nvme_qpair *qpair,
|
|
|
|
struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr,
|
|
|
|
bool print_on_error)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_cpl cpl;
|
|
|
|
|
|
|
|
memset(&cpl, 0, sizeof(cpl));
|
|
|
|
cpl.sqid = qpair->id;
|
|
|
|
cpl.cid = tr->cid;
|
|
|
|
cpl.status.sct = sct;
|
|
|
|
cpl.status.sc = sc;
|
|
|
|
cpl.status.dnr = dnr;
|
|
|
|
nvme_pcie_qpair_complete_tracker(qpair, tr, &cpl, print_on_error);
|
|
|
|
}
|
|
|
|
|
2016-10-21 22:37:18 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_qpair_abort_trackers(struct spdk_nvme_qpair *qpair, uint32_t dnr)
|
|
|
|
{
|
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
struct nvme_tracker *tr, *temp;
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
TAILQ_FOREACH_SAFE(tr, &pqpair->outstanding_tr, tq_list, temp) {
|
2016-10-21 22:37:18 +00:00
|
|
|
SPDK_ERRLOG("aborting outstanding command\n");
|
|
|
|
nvme_pcie_qpair_manual_complete_tracker(qpair, tr, SPDK_NVME_SCT_GENERIC,
|
|
|
|
SPDK_NVME_SC_ABORTED_BY_REQUEST, dnr, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
2016-10-13 22:23:55 +00:00
|
|
|
struct nvme_tracker *tr;
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
tr = TAILQ_FIRST(&pqpair->outstanding_tr);
|
2016-10-13 22:23:55 +00:00
|
|
|
while (tr != NULL) {
|
|
|
|
assert(tr->req != NULL);
|
|
|
|
if (tr->req->cmd.opc == SPDK_NVME_OPC_ASYNC_EVENT_REQUEST) {
|
|
|
|
nvme_pcie_qpair_manual_complete_tracker(qpair, tr,
|
|
|
|
SPDK_NVME_SCT_GENERIC, SPDK_NVME_SC_ABORTED_SQ_DELETION, 0,
|
|
|
|
false);
|
2016-12-10 22:39:54 +00:00
|
|
|
tr = TAILQ_FIRST(&pqpair->outstanding_tr);
|
2016-10-13 22:23:55 +00:00
|
|
|
} else {
|
2016-12-10 22:39:54 +00:00
|
|
|
tr = TAILQ_NEXT(tr, tq_list);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_admin_qpair_destroy(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
nvme_pcie_admin_qpair_abort_aers(qpair);
|
|
|
|
}
|
|
|
|
|
2016-11-28 22:25:05 +00:00
|
|
|
static int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_destroy(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
if (nvme_qpair_is_admin_queue(qpair)) {
|
|
|
|
nvme_pcie_admin_qpair_destroy(qpair);
|
|
|
|
}
|
2016-10-19 22:29:39 +00:00
|
|
|
if (pqpair->cmd && !pqpair->sq_in_cmb) {
|
|
|
|
spdk_free(pqpair->cmd);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
2016-10-19 22:29:39 +00:00
|
|
|
if (pqpair->cpl) {
|
|
|
|
spdk_free(pqpair->cpl);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
2016-10-19 22:29:39 +00:00
|
|
|
if (pqpair->tr) {
|
|
|
|
spdk_free(pqpair->tr);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
2016-11-03 22:34:35 +00:00
|
|
|
|
2016-11-28 22:25:05 +00:00
|
|
|
spdk_free(pqpair);
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
return 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_admin_qpair_enable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Manually abort each outstanding admin command. Do not retry
|
|
|
|
* admin commands found here, since they will be left over from
|
|
|
|
* a controller reset and its likely the context in which the
|
|
|
|
* command was issued no longer applies.
|
|
|
|
*/
|
2016-10-21 22:37:18 +00:00
|
|
|
nvme_pcie_qpair_abort_trackers(qpair, 1 /* do not retry */);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_io_qpair_enable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
/* Manually abort each outstanding I/O. */
|
2016-10-21 22:37:18 +00:00
|
|
|
nvme_pcie_qpair_abort_trackers(qpair, 0);
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_enable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
|
|
|
|
pqpair->is_enabled = true;
|
2016-10-13 22:23:55 +00:00
|
|
|
if (nvme_qpair_is_io_queue(qpair)) {
|
|
|
|
nvme_pcie_io_qpair_enable(qpair);
|
|
|
|
} else {
|
|
|
|
nvme_pcie_admin_qpair_enable(qpair);
|
|
|
|
}
|
2016-11-03 22:34:35 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_admin_qpair_disable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
nvme_pcie_admin_qpair_abort_aers(qpair);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nvme_pcie_io_qpair_disable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_disable(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
|
|
|
|
pqpair->is_enabled = false;
|
2016-10-13 22:23:55 +00:00
|
|
|
if (nvme_qpair_is_io_queue(qpair)) {
|
|
|
|
nvme_pcie_io_qpair_disable(qpair);
|
|
|
|
} else {
|
|
|
|
nvme_pcie_admin_qpair_disable(qpair);
|
|
|
|
}
|
2016-11-03 22:34:35 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_fail(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-21 22:37:18 +00:00
|
|
|
nvme_pcie_qpair_abort_trackers(qpair, 1 /* do not retry */);
|
2016-11-03 22:34:35 +00:00
|
|
|
|
|
|
|
return 0;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 00:04:48 +00:00
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_cmd_create_io_cq(struct spdk_nvme_ctrlr *ctrlr,
|
|
|
|
struct spdk_nvme_qpair *io_que, spdk_nvme_cmd_cb cb_fn,
|
|
|
|
void *cb_arg)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(io_que);
|
2016-10-14 00:04:48 +00:00
|
|
|
struct nvme_request *req;
|
|
|
|
struct spdk_nvme_cmd *cmd;
|
|
|
|
|
|
|
|
req = nvme_allocate_request_null(cb_fn, cb_arg);
|
|
|
|
if (req == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = &req->cmd;
|
|
|
|
cmd->opc = SPDK_NVME_OPC_CREATE_IO_CQ;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: create a create io completion queue command data
|
|
|
|
* structure.
|
|
|
|
*/
|
|
|
|
cmd->cdw10 = ((io_que->num_entries - 1) << 16) | io_que->id;
|
|
|
|
/*
|
|
|
|
* 0x2 = interrupts enabled
|
|
|
|
* 0x1 = physically contiguous
|
|
|
|
*/
|
|
|
|
cmd->cdw11 = 0x1;
|
2016-10-19 22:29:39 +00:00
|
|
|
cmd->dptr.prp.prp1 = pqpair->cpl_bus_addr;
|
2016-10-14 00:04:48 +00:00
|
|
|
|
|
|
|
return nvme_ctrlr_submit_admin_request(ctrlr, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_cmd_create_io_sq(struct spdk_nvme_ctrlr *ctrlr,
|
|
|
|
struct spdk_nvme_qpair *io_que, spdk_nvme_cmd_cb cb_fn, void *cb_arg)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(io_que);
|
2016-10-14 00:04:48 +00:00
|
|
|
struct nvme_request *req;
|
|
|
|
struct spdk_nvme_cmd *cmd;
|
|
|
|
|
|
|
|
req = nvme_allocate_request_null(cb_fn, cb_arg);
|
|
|
|
if (req == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = &req->cmd;
|
|
|
|
cmd->opc = SPDK_NVME_OPC_CREATE_IO_SQ;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: create a create io submission queue command data
|
|
|
|
* structure.
|
|
|
|
*/
|
|
|
|
cmd->cdw10 = ((io_que->num_entries - 1) << 16) | io_que->id;
|
|
|
|
/* 0x1 = physically contiguous */
|
|
|
|
cmd->cdw11 = (io_que->id << 16) | (io_que->qprio << 1) | 0x1;
|
2016-10-19 22:29:39 +00:00
|
|
|
cmd->dptr.prp.prp1 = pqpair->cmd_bus_addr;
|
2016-10-14 00:04:48 +00:00
|
|
|
|
|
|
|
return nvme_ctrlr_submit_admin_request(ctrlr, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_cmd_delete_io_cq(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair,
|
|
|
|
spdk_nvme_cmd_cb cb_fn, void *cb_arg)
|
|
|
|
{
|
|
|
|
struct nvme_request *req;
|
|
|
|
struct spdk_nvme_cmd *cmd;
|
|
|
|
|
|
|
|
req = nvme_allocate_request_null(cb_fn, cb_arg);
|
|
|
|
if (req == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = &req->cmd;
|
|
|
|
cmd->opc = SPDK_NVME_OPC_DELETE_IO_CQ;
|
|
|
|
cmd->cdw10 = qpair->id;
|
|
|
|
|
|
|
|
return nvme_ctrlr_submit_admin_request(ctrlr, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nvme_pcie_ctrlr_cmd_delete_io_sq(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair,
|
|
|
|
spdk_nvme_cmd_cb cb_fn, void *cb_arg)
|
|
|
|
{
|
|
|
|
struct nvme_request *req;
|
|
|
|
struct spdk_nvme_cmd *cmd;
|
|
|
|
|
|
|
|
req = nvme_allocate_request_null(cb_fn, cb_arg);
|
|
|
|
if (req == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = &req->cmd;
|
|
|
|
cmd->opc = SPDK_NVME_OPC_DELETE_IO_SQ;
|
|
|
|
cmd->cdw10 = qpair->id;
|
|
|
|
|
|
|
|
return nvme_ctrlr_submit_admin_request(ctrlr, req);
|
|
|
|
}
|
|
|
|
|
2016-10-13 00:33:37 +00:00
|
|
|
static int
|
2016-10-18 16:49:07 +00:00
|
|
|
_nvme_pcie_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair,
|
|
|
|
uint16_t qid)
|
2016-10-13 00:33:37 +00:00
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
2016-10-18 16:49:07 +00:00
|
|
|
int rc;
|
2016-10-13 00:33:37 +00:00
|
|
|
|
|
|
|
status.done = false;
|
2016-10-14 00:04:48 +00:00
|
|
|
rc = nvme_pcie_ctrlr_cmd_create_io_cq(ctrlr, qpair, nvme_completion_poll_cb, &status);
|
2016-10-13 00:33:37 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (status.done == false) {
|
2016-10-19 17:19:34 +00:00
|
|
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
2016-10-13 00:33:37 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
|
|
SPDK_ERRLOG("nvme_create_io_cq failed!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
status.done = false;
|
2016-10-14 00:04:48 +00:00
|
|
|
rc = nvme_pcie_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair, nvme_completion_poll_cb, &status);
|
2016-10-13 00:33:37 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (status.done == false) {
|
2016-10-19 17:19:34 +00:00
|
|
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
2016-10-13 00:33:37 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
|
|
SPDK_ERRLOG("nvme_create_io_sq failed!\n");
|
|
|
|
/* Attempt to delete the completion queue */
|
|
|
|
status.done = false;
|
2016-10-14 00:04:48 +00:00
|
|
|
rc = nvme_pcie_ctrlr_cmd_delete_io_cq(qpair->ctrlr, qpair, nvme_completion_poll_cb, &status);
|
2016-10-13 00:33:37 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
while (status.done == false) {
|
2016-10-19 17:19:34 +00:00
|
|
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
2016-10-13 00:33:37 +00:00
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_reset(qpair);
|
2016-10-13 00:33:37 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
struct spdk_nvme_qpair *
|
2016-10-18 16:49:07 +00:00
|
|
|
nvme_pcie_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid,
|
|
|
|
enum spdk_nvme_qprio qprio)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair;
|
2016-10-18 16:49:07 +00:00
|
|
|
struct spdk_nvme_qpair *qpair;
|
|
|
|
uint32_t num_entries;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
assert(ctrlr != NULL);
|
|
|
|
|
2016-11-07 06:35:48 +00:00
|
|
|
pqpair = spdk_zmalloc(sizeof(*pqpair), 64, NULL);
|
2016-10-19 22:29:39 +00:00
|
|
|
if (pqpair == NULL) {
|
2016-10-18 16:49:07 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
qpair = &pqpair->qpair;
|
|
|
|
|
2016-10-18 16:49:07 +00:00
|
|
|
/*
|
|
|
|
* NVMe spec sets a hard limit of 64K max entries, but
|
|
|
|
* devices may specify a smaller limit, so we need to check
|
|
|
|
* the MQES field in the capabilities register.
|
|
|
|
*/
|
2016-10-19 20:18:27 +00:00
|
|
|
num_entries = nvme_min(NVME_IO_ENTRIES, ctrlr->cap.bits.mqes + 1);
|
2016-10-18 16:49:07 +00:00
|
|
|
|
2016-11-29 05:18:30 +00:00
|
|
|
/* Also should choose minmal between original and the value passed by users */
|
|
|
|
num_entries = nvme_min(num_entries, ctrlr->opts.queue_size);
|
|
|
|
|
2016-10-26 01:28:20 +00:00
|
|
|
rc = nvme_qpair_construct(qpair, qid, num_entries, ctrlr, qprio);
|
2016-10-18 16:49:07 +00:00
|
|
|
if (rc != 0) {
|
2016-11-28 22:25:05 +00:00
|
|
|
nvme_pcie_qpair_destroy(qpair);
|
2016-10-18 16:49:07 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = _nvme_pcie_ctrlr_create_io_qpair(ctrlr, qpair, qid);
|
|
|
|
|
|
|
|
if (rc != 0) {
|
2016-11-03 08:50:16 +00:00
|
|
|
SPDK_ERRLOG("I/O queue creation failed\n");
|
2016-11-28 22:25:05 +00:00
|
|
|
nvme_pcie_qpair_destroy(qpair);
|
2016-10-18 16:49:07 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return qpair;
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-18 16:49:07 +00:00
|
|
|
nvme_pcie_ctrlr_reinit_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
return _nvme_pcie_ctrlr_create_io_qpair(ctrlr, qpair, qpair->id);
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 00:33:37 +00:00
|
|
|
nvme_pcie_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
|
|
|
struct nvme_completion_poll_status status;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
assert(ctrlr != NULL);
|
|
|
|
|
2016-11-18 15:52:43 +00:00
|
|
|
if (ctrlr->is_removed) {
|
|
|
|
goto free;
|
|
|
|
}
|
|
|
|
|
2016-10-13 00:33:37 +00:00
|
|
|
/* Delete the I/O submission queue and then the completion queue */
|
|
|
|
|
|
|
|
status.done = false;
|
2016-10-14 00:04:48 +00:00
|
|
|
rc = nvme_pcie_ctrlr_cmd_delete_io_sq(ctrlr, qpair, nvme_completion_poll_cb, &status);
|
2016-10-13 00:33:37 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
while (status.done == false) {
|
2016-10-19 17:19:34 +00:00
|
|
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
2016-10-13 00:33:37 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
status.done = false;
|
2016-10-14 00:04:48 +00:00
|
|
|
rc = nvme_pcie_ctrlr_cmd_delete_io_cq(ctrlr, qpair, nvme_completion_poll_cb, &status);
|
2016-10-13 00:33:37 +00:00
|
|
|
if (rc != 0) {
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
while (status.done == false) {
|
2016-10-19 17:19:34 +00:00
|
|
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
2016-10-13 00:33:37 +00:00
|
|
|
}
|
|
|
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-11-18 15:52:43 +00:00
|
|
|
free:
|
2016-11-28 22:25:05 +00:00
|
|
|
nvme_pcie_qpair_destroy(qpair);
|
2016-10-13 00:33:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
static void
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(struct spdk_nvme_qpair *qpair, struct nvme_tracker *tr)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Bad vtophys translation, so abort this request and return
|
|
|
|
* immediately.
|
|
|
|
*/
|
|
|
|
nvme_pcie_qpair_manual_complete_tracker(qpair, tr, SPDK_NVME_SCT_GENERIC,
|
|
|
|
SPDK_NVME_SC_INVALID_FIELD,
|
|
|
|
1 /* do not retry */, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Build PRP list describing physically contiguous payload buffer.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
nvme_pcie_qpair_build_contig_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req,
|
|
|
|
struct nvme_tracker *tr)
|
|
|
|
{
|
|
|
|
uint64_t phys_addr;
|
|
|
|
void *seg_addr;
|
|
|
|
uint32_t nseg, cur_nseg, modulo, unaligned;
|
|
|
|
void *md_payload;
|
|
|
|
void *payload = req->payload.u.contig + req->payload_offset;
|
|
|
|
|
|
|
|
phys_addr = spdk_vtophys(payload);
|
|
|
|
if (phys_addr == SPDK_VTOPHYS_ERROR) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
nseg = req->payload_size >> nvme_u32log2(PAGE_SIZE);
|
|
|
|
modulo = req->payload_size & (PAGE_SIZE - 1);
|
|
|
|
unaligned = phys_addr & (PAGE_SIZE - 1);
|
|
|
|
if (modulo || unaligned) {
|
|
|
|
nseg += 1 + ((modulo + unaligned - 1) >> nvme_u32log2(PAGE_SIZE));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req->payload.md) {
|
|
|
|
md_payload = req->payload.md + req->md_offset;
|
|
|
|
tr->req->cmd.mptr = spdk_vtophys(md_payload);
|
|
|
|
if (tr->req->cmd.mptr == SPDK_VTOPHYS_ERROR) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tr->req->cmd.psdt = SPDK_NVME_PSDT_PRP;
|
|
|
|
tr->req->cmd.dptr.prp.prp1 = phys_addr;
|
|
|
|
if (nseg == 2) {
|
|
|
|
seg_addr = payload + PAGE_SIZE - unaligned;
|
|
|
|
tr->req->cmd.dptr.prp.prp2 = spdk_vtophys(seg_addr);
|
|
|
|
} else if (nseg > 2) {
|
|
|
|
cur_nseg = 1;
|
|
|
|
tr->req->cmd.dptr.prp.prp2 = (uint64_t)tr->prp_sgl_bus_addr;
|
|
|
|
while (cur_nseg < nseg) {
|
|
|
|
seg_addr = payload + cur_nseg * PAGE_SIZE - unaligned;
|
|
|
|
phys_addr = spdk_vtophys(seg_addr);
|
|
|
|
if (phys_addr == SPDK_VTOPHYS_ERROR) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
tr->u.prp[cur_nseg - 1] = phys_addr;
|
|
|
|
cur_nseg++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Build SGL list describing scattered payload buffer.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
nvme_pcie_qpair_build_hw_sgl_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req,
|
|
|
|
struct nvme_tracker *tr)
|
|
|
|
{
|
|
|
|
int rc;
|
2016-11-03 17:12:16 +00:00
|
|
|
void *virt_addr;
|
2016-10-13 22:23:55 +00:00
|
|
|
uint64_t phys_addr;
|
|
|
|
uint32_t remaining_transfer_len, length;
|
|
|
|
struct spdk_nvme_sgl_descriptor *sgl;
|
|
|
|
uint32_t nseg = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Build scattered payloads.
|
|
|
|
*/
|
|
|
|
assert(req->payload_size != 0);
|
|
|
|
assert(req->payload.type == NVME_PAYLOAD_TYPE_SGL);
|
|
|
|
assert(req->payload.u.sgl.reset_sgl_fn != NULL);
|
|
|
|
assert(req->payload.u.sgl.next_sge_fn != NULL);
|
|
|
|
req->payload.u.sgl.reset_sgl_fn(req->payload.u.sgl.cb_arg, req->payload_offset);
|
|
|
|
|
|
|
|
sgl = tr->u.sgl;
|
|
|
|
req->cmd.psdt = SPDK_NVME_PSDT_SGL_MPTR_SGL;
|
|
|
|
req->cmd.dptr.sgl1.unkeyed.subtype = 0;
|
|
|
|
|
|
|
|
remaining_transfer_len = req->payload_size;
|
|
|
|
|
|
|
|
while (remaining_transfer_len > 0) {
|
|
|
|
if (nseg >= NVME_MAX_SGL_DESCRIPTORS) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-11-03 17:12:16 +00:00
|
|
|
rc = req->payload.u.sgl.next_sge_fn(req->payload.u.sgl.cb_arg, &virt_addr, &length);
|
2016-10-13 22:23:55 +00:00
|
|
|
if (rc) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-11-03 17:12:16 +00:00
|
|
|
phys_addr = spdk_vtophys(virt_addr);
|
|
|
|
if (phys_addr == SPDK_VTOPHYS_ERROR) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
length = nvme_min(remaining_transfer_len, length);
|
|
|
|
remaining_transfer_len -= length;
|
|
|
|
|
|
|
|
sgl->unkeyed.type = SPDK_NVME_SGL_TYPE_DATA_BLOCK;
|
|
|
|
sgl->unkeyed.length = length;
|
|
|
|
sgl->address = phys_addr;
|
|
|
|
sgl->unkeyed.subtype = 0;
|
|
|
|
|
|
|
|
sgl++;
|
|
|
|
nseg++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nseg == 1) {
|
|
|
|
/*
|
|
|
|
* The whole transfer can be described by a single SGL descriptor.
|
|
|
|
* Use the special case described by the spec where SGL1's type is Data Block.
|
|
|
|
* This means the SGL in the tracker is not used at all, so copy the first (and only)
|
|
|
|
* SGL element into SGL1.
|
|
|
|
*/
|
|
|
|
req->cmd.dptr.sgl1.unkeyed.type = SPDK_NVME_SGL_TYPE_DATA_BLOCK;
|
|
|
|
req->cmd.dptr.sgl1.address = tr->u.sgl[0].address;
|
|
|
|
req->cmd.dptr.sgl1.unkeyed.length = tr->u.sgl[0].unkeyed.length;
|
|
|
|
} else {
|
|
|
|
/* For now we can only support 1 SGL segment in NVMe controller */
|
|
|
|
req->cmd.dptr.sgl1.unkeyed.type = SPDK_NVME_SGL_TYPE_LAST_SEGMENT;
|
|
|
|
req->cmd.dptr.sgl1.address = tr->prp_sgl_bus_addr;
|
|
|
|
req->cmd.dptr.sgl1.unkeyed.length = nseg * sizeof(struct spdk_nvme_sgl_descriptor);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Build PRP list describing scattered payload buffer.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
nvme_pcie_qpair_build_prps_sgl_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req,
|
|
|
|
struct nvme_tracker *tr)
|
|
|
|
{
|
|
|
|
int rc;
|
2016-11-03 17:12:16 +00:00
|
|
|
void *virt_addr;
|
2016-10-13 22:23:55 +00:00
|
|
|
uint64_t phys_addr;
|
|
|
|
uint32_t data_transferred, remaining_transfer_len, length;
|
|
|
|
uint32_t nseg, cur_nseg, total_nseg, last_nseg, modulo, unaligned;
|
|
|
|
uint32_t sge_count = 0;
|
|
|
|
uint64_t prp2 = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Build scattered payloads.
|
|
|
|
*/
|
|
|
|
assert(req->payload.type == NVME_PAYLOAD_TYPE_SGL);
|
|
|
|
assert(req->payload.u.sgl.reset_sgl_fn != NULL);
|
|
|
|
req->payload.u.sgl.reset_sgl_fn(req->payload.u.sgl.cb_arg, req->payload_offset);
|
|
|
|
|
|
|
|
remaining_transfer_len = req->payload_size;
|
|
|
|
total_nseg = 0;
|
|
|
|
last_nseg = 0;
|
|
|
|
|
|
|
|
while (remaining_transfer_len > 0) {
|
|
|
|
assert(req->payload.u.sgl.next_sge_fn != NULL);
|
2016-11-03 17:12:16 +00:00
|
|
|
rc = req->payload.u.sgl.next_sge_fn(req->payload.u.sgl.cb_arg, &virt_addr, &length);
|
2016-10-13 22:23:55 +00:00
|
|
|
if (rc) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-11-03 17:12:16 +00:00
|
|
|
phys_addr = spdk_vtophys(virt_addr);
|
|
|
|
if (phys_addr == SPDK_VTOPHYS_ERROR) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
/* Confirm that this sge is prp compatible. */
|
|
|
|
if (phys_addr & 0x3 ||
|
|
|
|
(length < remaining_transfer_len && ((phys_addr + length) & (PAGE_SIZE - 1)))) {
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
data_transferred = nvme_min(remaining_transfer_len, length);
|
|
|
|
|
|
|
|
nseg = data_transferred >> nvme_u32log2(PAGE_SIZE);
|
|
|
|
modulo = data_transferred & (PAGE_SIZE - 1);
|
|
|
|
unaligned = phys_addr & (PAGE_SIZE - 1);
|
|
|
|
if (modulo || unaligned) {
|
|
|
|
nseg += 1 + ((modulo + unaligned - 1) >> nvme_u32log2(PAGE_SIZE));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (total_nseg == 0) {
|
|
|
|
req->cmd.psdt = SPDK_NVME_PSDT_PRP;
|
|
|
|
req->cmd.dptr.prp.prp1 = phys_addr;
|
|
|
|
phys_addr -= unaligned;
|
|
|
|
}
|
|
|
|
|
|
|
|
total_nseg += nseg;
|
|
|
|
sge_count++;
|
|
|
|
remaining_transfer_len -= data_transferred;
|
|
|
|
|
|
|
|
if (total_nseg == 2) {
|
|
|
|
if (sge_count == 1)
|
|
|
|
tr->req->cmd.dptr.prp.prp2 = phys_addr + PAGE_SIZE;
|
|
|
|
else if (sge_count == 2)
|
|
|
|
tr->req->cmd.dptr.prp.prp2 = phys_addr;
|
|
|
|
/* save prp2 value */
|
|
|
|
prp2 = tr->req->cmd.dptr.prp.prp2;
|
|
|
|
} else if (total_nseg > 2) {
|
|
|
|
if (sge_count == 1)
|
|
|
|
cur_nseg = 1;
|
|
|
|
else
|
|
|
|
cur_nseg = 0;
|
|
|
|
|
|
|
|
tr->req->cmd.dptr.prp.prp2 = (uint64_t)tr->prp_sgl_bus_addr;
|
|
|
|
while (cur_nseg < nseg) {
|
|
|
|
if (prp2) {
|
|
|
|
tr->u.prp[0] = prp2;
|
|
|
|
tr->u.prp[last_nseg + 1] = phys_addr + cur_nseg * PAGE_SIZE;
|
|
|
|
} else
|
|
|
|
tr->u.prp[last_nseg] = phys_addr + cur_nseg * PAGE_SIZE;
|
|
|
|
|
|
|
|
last_nseg++;
|
|
|
|
cur_nseg++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
nvme_pcie_qpair_check_enabled(struct spdk_nvme_qpair *qpair)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
|
|
|
|
|
|
|
if (!pqpair->is_enabled &&
|
2016-10-13 22:23:55 +00:00
|
|
|
!qpair->ctrlr->is_resetting) {
|
|
|
|
nvme_qpair_enable(qpair);
|
|
|
|
}
|
2016-10-19 22:29:39 +00:00
|
|
|
return pqpair->is_enabled;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req)
|
|
|
|
{
|
2016-11-22 09:31:46 +00:00
|
|
|
struct nvme_tracker *tr;
|
|
|
|
int rc = 0;
|
|
|
|
struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
|
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
nvme_pcie_qpair_check_enabled(qpair);
|
|
|
|
|
2016-11-22 09:31:46 +00:00
|
|
|
if (nvme_qpair_is_admin_queue(qpair)) {
|
2016-12-05 20:54:16 +00:00
|
|
|
nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-11-22 09:31:46 +00:00
|
|
|
}
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
tr = TAILQ_FIRST(&pqpair->free_tr);
|
2016-10-13 22:23:55 +00:00
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (tr == NULL || !pqpair->is_enabled) {
|
2016-10-13 22:23:55 +00:00
|
|
|
/*
|
|
|
|
* No tracker is available, or the qpair is disabled due to
|
|
|
|
* an in-progress controller-level reset.
|
|
|
|
*
|
|
|
|
* Put the request on the qpair's request queue to be
|
|
|
|
* processed when a tracker frees up via a command
|
|
|
|
* completion or when the controller reset is
|
|
|
|
* completed.
|
|
|
|
*/
|
|
|
|
STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq);
|
2016-11-22 09:31:46 +00:00
|
|
|
goto exit;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-12-10 22:39:54 +00:00
|
|
|
TAILQ_REMOVE(&pqpair->free_tr, tr, tq_list); /* remove tr from free_tr */
|
|
|
|
TAILQ_INSERT_HEAD(&pqpair->outstanding_tr, tr, tq_list);
|
2016-10-13 22:23:55 +00:00
|
|
|
tr->req = req;
|
|
|
|
req->cmd.cid = tr->cid;
|
|
|
|
|
|
|
|
if (req->payload_size == 0) {
|
|
|
|
/* Null payload - leave PRP fields zeroed */
|
|
|
|
rc = 0;
|
|
|
|
} else if (req->payload.type == NVME_PAYLOAD_TYPE_CONTIG) {
|
|
|
|
rc = nvme_pcie_qpair_build_contig_request(qpair, req, tr);
|
|
|
|
} else if (req->payload.type == NVME_PAYLOAD_TYPE_SGL) {
|
|
|
|
if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) {
|
|
|
|
rc = nvme_pcie_qpair_build_hw_sgl_request(qpair, req, tr);
|
|
|
|
} else {
|
|
|
|
rc = nvme_pcie_qpair_build_prps_sgl_request(qpair, req, tr);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
assert(0);
|
|
|
|
nvme_pcie_fail_request_bad_vtophys(qpair, tr);
|
|
|
|
rc = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rc < 0) {
|
2016-11-22 09:31:46 +00:00
|
|
|
goto exit;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
nvme_pcie_qpair_submit_tracker(qpair, tr);
|
2016-11-22 09:31:46 +00:00
|
|
|
|
|
|
|
exit:
|
|
|
|
if (nvme_qpair_is_admin_queue(qpair)) {
|
2016-12-05 20:54:16 +00:00
|
|
|
nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-11-22 09:31:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:34:35 +00:00
|
|
|
int32_t
|
2016-10-13 22:23:55 +00:00
|
|
|
nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_completions)
|
|
|
|
{
|
2016-10-19 22:29:39 +00:00
|
|
|
struct nvme_pcie_qpair *pqpair = nvme_pcie_qpair(qpair);
|
2016-11-15 02:33:24 +00:00
|
|
|
struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(qpair->ctrlr);
|
2016-10-13 22:23:55 +00:00
|
|
|
struct nvme_tracker *tr;
|
|
|
|
struct spdk_nvme_cpl *cpl;
|
2016-11-22 09:31:46 +00:00
|
|
|
uint32_t num_completions = 0;
|
|
|
|
struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
if (!nvme_pcie_qpair_check_enabled(qpair)) {
|
|
|
|
/*
|
|
|
|
* qpair is not enabled, likely because a controller reset is
|
|
|
|
* is in progress. Ignore the interrupt - any I/O that was
|
|
|
|
* associated with this interrupt will get retried when the
|
|
|
|
* reset is complete.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-22 09:31:46 +00:00
|
|
|
if (nvme_qpair_is_admin_queue(qpair)) {
|
2016-12-05 20:54:16 +00:00
|
|
|
nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
|
2016-11-22 09:31:46 +00:00
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
if (max_completions == 0 || (max_completions > (qpair->num_entries - 1U))) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* max_completions == 0 means unlimited, but complete at most one
|
|
|
|
* queue depth batch of I/O at a time so that the completion
|
|
|
|
* queue doorbells don't wrap around.
|
|
|
|
*/
|
|
|
|
max_completions = qpair->num_entries - 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (1) {
|
2016-10-19 22:29:39 +00:00
|
|
|
cpl = &pqpair->cpl[pqpair->cq_head];
|
2016-10-13 22:23:55 +00:00
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (cpl->status.p != pqpair->phase)
|
2016-10-13 22:23:55 +00:00
|
|
|
break;
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
tr = &pqpair->tr[cpl->cid];
|
2016-10-13 22:23:55 +00:00
|
|
|
|
|
|
|
if (tr->active) {
|
|
|
|
nvme_pcie_qpair_complete_tracker(qpair, tr, cpl, true);
|
|
|
|
} else {
|
|
|
|
SPDK_ERRLOG("cpl does not map to outstanding cmd\n");
|
|
|
|
nvme_qpair_print_completion(qpair, cpl);
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
|
2016-10-19 22:29:39 +00:00
|
|
|
if (++pqpair->cq_head == qpair->num_entries) {
|
|
|
|
pqpair->cq_head = 0;
|
|
|
|
pqpair->phase = !pqpair->phase;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (++num_completions == max_completions) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_completions > 0) {
|
2016-11-15 02:33:24 +00:00
|
|
|
g_thread_mmio_ctrlr = pctrlr;
|
2016-10-19 22:29:39 +00:00
|
|
|
spdk_mmio_write_4(pqpair->cq_hdbl, pqpair->cq_head);
|
2016-11-15 02:33:24 +00:00
|
|
|
g_thread_mmio_ctrlr = NULL;
|
2016-10-13 22:23:55 +00:00
|
|
|
}
|
|
|
|
|
2016-10-18 01:03:24 +00:00
|
|
|
/* Before returning, complete any pending admin request. */
|
|
|
|
if (nvme_qpair_is_admin_queue(qpair)) {
|
|
|
|
nvme_pcie_qpair_complete_pending_admin_request(qpair);
|
2016-11-22 09:31:46 +00:00
|
|
|
|
2016-12-05 20:54:16 +00:00
|
|
|
nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
|
2016-10-18 01:03:24 +00:00
|
|
|
}
|
|
|
|
|
2016-10-13 22:23:55 +00:00
|
|
|
return num_completions;
|
|
|
|
}
|